Call number: LD2668 .T4 1984 R428 / Master of Science

Call number: LD2668 .T4 1985 D63 / Master of Science

Call number: LD2668 .T4 1985 S246 / Master of Science

Power consumption is a critical issue for portable devices. The ever-increasing demand for multimode wireless applications and the growing concerns towards power-aware green technology make dynamically reconfigurable hardware an attractive solution for overcoming the power issue. This is due to its advantages of flexibility, reusability, and adaptability. During the last decade, reconfigurable analog-to-digital converters (ReADCs) have been used to support multimode wireless applications. With the ability to adaptively scale the power consumption according to different operation modes, reconfigurable devices utilise the power supply efficiently. This can prolong battery life and reduce unnecessary heat emission to the environment. However, current adaptive mechanisms for ReADCs rely upon external control signals generated using digital signal processors (DSPs) in the baseband. This thesis aims to provide a single-chip solution for real-time and low-power ReADC implementations that can adaptively change the converter resolution according to signal variations without the need of the baseband processing. Specifically, the thesis focuses on the analysis, design and implementation of a low-power digital controller unit for ReADCs. In this study, the following two important reconfigurability issues are investigated: i) the detection mechanism for an adaptive implementation, and ii) the measure of power and area overheads that are introduced by the adaptive control modules. This thesis outlines four main achievements to address these issues. The first achievement is the development of the switching activity measurement (SWAM) method to detect different signal components based upon the observation of the output of an ADC. The second achievement is a proposed adaptive algorithm for ReADCs to dynamically adjust the resolution depending upon the variations in the input signal. The third achievement is an ASIC implementation of the adaptive control module for ReADCs. The module achieves low reconfiguration overheads in terms of area and power compared with the main analog part of a ReADC. The fourth achievement is the development of a low-power noise detection module using a conventional ADC for signal improvement. Taken together, the findings from this study demonstrate the potential use of switching activity information of an ADC to adaptively control the circuits, and simultaneously expanding the functionality of the ADC in electronic systems.

The objective of this research is to optimize silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) BiCMOS analog circuit building blocks for operation in extreme environments utilizing design techniques. First, negative feedback effects on single-event transient (SET) in SiGe HBT analog circuits were investigated. In order to study the role of internal and external negative feedback effects on SET in circuits, two different types of current mirrors (a basic common-emitter current mirror and a Wilson current mirror) were fabricated using a SiGe HBT BiCMOS technology and exposed to laser-induced single events. The SET measurements were performed at the U.S. Naval Research Laboratory using a two-photon absorption (TPA) pulsed laser. The measured data showed that negative feedback improved SET response in the analog circuits; the highest peak output transient current was reduced by more than 50%, and the settling time of the output current upon a TPA laser strike was shortened with negative feedback. This proven negative feedback radiation hardening technique was applied later in the high-speed 5-bit flash analog-to-digital converter (ADC) for receiver chains of radar systems to improve SET response of the system.

Thesis (PhD)--University of Stellenbosch, 2004. / ENGLISH ABSTRACT: Analog-to-digital converters (ADCs) are an integral part of the interface between the analog and digital realms. This dissertation presents the design and simulation of a Complementary Output Switching-Logic (COSL) compatible, voltage state, switching logic comparator and a flash ADC for high speed applications with multi-GHz input bandwidth. Josephson technology and the COSL family of gates were utilized for this purpose. A detailed design for the switching logic comparator is first provided. The design is verified with simulations to obtain a functional comparator. The comparator is then optimized utilizing an optimization tool developed using the scripting facilities of WRSpice. Incorporated in this tool is a Monte Carlo capability to randomly vary the component values according to Gaussian distributions, and trimming facilities to be able to trim a non-functional comparator to restore functionality. The design component values are then optimized by maximizing the yield of a comparator. The optimized comparator is incorporated into the construction of a4-bit quantizer of an ADC. The output from the quantizer section yields a switching-logic Gray-code output. A Gray-to- Binary converter is designed with COSL gates to convert the Gray output from the quantizer into Binary code for further processing. The functionality, linearity, maximum input bandwidth and dynamic range of the 4-bit ADC is verified by simulation. A number of special input waveforms are used for this purpose. The performance of the comparator and the 4-bit ADC is also evaluated with thermal noise incorporated into simulation. Beat frequency simulations and Fourier spectra were also used in the evaluation of the ADC performance. A fully functional 4-bit ADC, with a maximum input bandwidth of 10 GHz for a clock speed of 20 GHz was achieved through simulations. Beat frequency simulations revealed that the comparators have an input bandwidth greater than 19 GHz with sufficient dynamic range for an ADC of greater than 6 bits of resolution. Due to the fact that the aperture time for the ADC is dependant on the rise time of the sampling pulse and not the width of the pulse, a much smaller aperture time is obtained which directly translates to higher input bandwidth. Finally, a layout of a 4-bit sampler circuit was done according to the Hypres manufacturing process to enable the high-speed testing of the comparator circuits. / AFRIKAANSE OPSOMMING: Analoog-na-Digitale Omsetters (ADOs) vorm 'n integrale deel van die koppelvlak tussen die analoog en digitale wêrelde. Hiedie proefskrif stel die ontwerp en simulasie van 'n Komplementêre Uittree Geskakelde Logika (COSL) aanpasbare, spanningstoestand, geskakelde logika vergelyker en ADO bekend. Hierdie ADO kan vir hoë spoed toepassings waar multi-GHz intree-bandwydte benodig word, aangewend word. Josephson tegnologie en die Komplementêre Uittree Geskakelde Logika (COSL) familie van hekke word vir hierdie doel gebruik. Die volledige ontwerp vir die geskakelde logika vergelyker word eerstens gegee. Die ontwerp word met behulp van simulasies bevestig om sodoende 'n ten volle funksionele vergelyker te verkry. Die vergelyker word verder geëptimeer deur middel van 'n proses wat met behulp van programmering in WRSpice ontwikkel is. Hierdie optimeringsproses sluit 'n Monte Carlo proses in wat die komponentwaardes van die vergelyker onwillekeurig volgens 'n Gaussiese verspreiding verander, sowel as 'n verstellingsmeganisme waarmee 'n nie-funksionerende vergelyker verstel kan word totdat dit weer ten volle funksioneer. Die komponentwaardes word dan geëptimeer vir maksimale opbrengs van 'n vergelyker. Die geëptimeerde vergelyker word gebruik in die konstruksie van 'n 4-bis kwantifiseerder vir 'n ADO. Die uittree van die 4-bis kwantifiseerder is in Gray kode. 'n Gray-na-Binêre kode omsetter word vir hierdie doelontwerp deur van COSL hekke gebruik te maak. Die volle ADO word voorts gesimuleer om die funksionalitet, lineariteit, maksimum intreebandwydte en dinamiese bereik te verifieer. 'n Verskeidenheid van intreeseine is vir hierdie doel gebruik. Die vergelyker en die 4-bis ADO is ook gesimuleer met termiese ruis om die effek daarvan te bepaal. Fourier spektra en ''verskilfrekwensie'' (Beat Frequency) simulasies word ook gebruik in die evaluering van die vergelyker en die ADO. Die korrekte werking van 'n 4-bis ADO met intreebandwydte van 10 GHz met 'n klokspoed van 20 GHz is deur simulasie bevestig. Verskilfrekwensie simulasies dui aan dat die vergelykers 'n intreebandwydte van groter as 19 GHz het, met voldoende dinamiese bereik vir 6 bis resolusie. Aangesien die vergelykers se venstertydperk bepaal word deur die stygende helling van die monsterpuls en nie deur die pulswydte nie, maak dit voorsiening vir 'n baie klein venstertydperk. 'n Klein venstertydperk is essensieel vir 'n hoë intreebandwydte. 'n Uitleg van 'n 4-bis vergelyker stadium is gedoen vir die Hypres vervaardigingsproses om die vergelyker teen hoë spoed te kan toets.

published_or_final_version / Electrical and Electronic Engineering / Doctoral / Doctor of Philosophy

This thesis reports on the design and evaluation of a microprocessor-controlled, high-speed analog-to-digital converter. The processor supervises and manages the digital conversion, split-phase encoding (Manchester) and framing of the input signal. This converter is designed to be applied in an underwater package which will serially transmit sensor data over a fiber optic link to a shore station. This intelligent sensor will provide for ease of future system enhancements. An example would be the implementation of one package to multiplex several analog channels from a local sensor network over the single fiber optic link to the shore station. Keywords: Analog-to-Digital converter, Digital conversion, Split phase encoding, and Manchester. (r.h.) / http://archive.org/details/microprocessorco00schl / U.S. Coast Guard (U.S.C.G.) author.

Wang Hongwei. / "February 2001." / Thesis (Ph.D.)--Chinese University of Hong Kong, 2001. / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Electronic reproduction. Ann Arbor, MI : ProQuest Information and Learning Company, [200-] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Mode of access: World Wide Web. / Abstracts in English and Chinese.

Sun, Lei. / Thesis (Ph.D.)--Chinese University of Hong Kong, 2013. / Includes bibliographical references. / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Abstract also in Chinese.