The precise measurement of a capacitance difference or ratio in a digital form is very important for capacitive sensors, for CMOS process characterization as well as for the realization of precise switched-capacitor data converters, amplifiers and other circuits utilizing ratioed capacitors. This thesis introduces design techniques for on-chip capacitor ratio testing and sensor readout that utilize sigma-delta modulation and integrate the sensor capacitors into the modulator. Several single-ended circuits are introduced, and the correlated-double-sampling (CDS) technique is used in the circuits to reduce the non-ideal effects of opamps. Several simple calibration schemes for clock-feedthrough cancellation are also introduced and discussed. A fully-differential implementation is also described and various common-mode feedback schemes are discussed and analyzed. Simulation and experimental results show that these circuits can provide extremely accurate results even in the presence of non-ideal circuit effects such as finite opamp gain, opamp input offset and noise, and clock-feedthrough effect from the switches. To verify the effectiveness of the circuits and simulations, two prototype chips containing a single-ended realization and a fully-differential one were designed and fabricated in a 1.2 ��m CMOS technology. Two off-chip mica capacitors were used in the test circuits, and the measured results show that very accurate results can be obtained using these circuit techniques even with off-chip noise coupling and large parasitic capacitances. / Graduation date: 1999

Oversampled delta-sigma modulation is one of the widely used A/D conversion techniques for narrow bandwidth signals. In this study several new lowpass and bandpass delta-sigma modulator architectures as well as novel pseudo-N-path integrators that can be used in implementing these architectures are proposed. By using multiplexing techniques the new lowpass delta-sigma modulator architectures exchange higher clock rates with hardware complexity. For a given oversampling ratio (OSR), the multiplexed first-order delta-sigma modulator achieves a higher resolution. Guaranteed stability is a very desirable feature of these structures. The multi-loop delta-sigma modulator architecture similarly reduces the number of integrators needed to achieve high-resolution conversion for a given OSR. To ensure stability a quantizer with (N+1) bits must be used, where N is the number of loops, or in other words, the order of the delta-sigma modulator. Digital correction or randomizing techniques can be used to eliminate the performance reduction due to digital-to-analog- (D/A) converter nonlinearity error [59], [64]. Bandpass delta-sigma modulators are useful for applications such as AM radio receivers, spectrum analyzers, and digital wireless systems. Using z --> -z[superscript N] or z --> z[superscript N] mapping, a low pass delta-sigma modulator can be transformed to a bandpass one. One of the methods to implement the loop filters in bandpass delta-sigma modulators is to use Pseudo-N-Path (PNP) switched-capacitor (SC) integrators. The advantage is that the center frequency occurs exactly at an integer division of the sampling frequency because of the number of physical paths. To achieve maximum resolution, integrators that do not suffer from clock feedthrough peaks are needed. The proposed differential and single-ended novel PNP integrators address this problem [76]. To keep the opamp specifications less stringent while achieving high resolution, these PNP integrators have been further improved with gain compensation techniques [53]. / Graduation date: 1997

Graduation date: 1995

Graduation date: 1994

Graduation date: 1993

The continued speed improvement of serial links and appearance of new communication technologies, such as ultra wideband (UWB), have introduced increasing demands on the speed and power specifications of high speed low to medium resolution analog to digital converters (ADCs). While multi channel ADCs can achieve high speeds, they often require extensive and costly post fabrication calibration. A single channel 4 bit flash ADC, suitable for abovementioned or similar applications, implemented entirely using current mode logic (CML) blocks, is presented. CML implementation allows for high sampling rates, while typically providing low power consumption at high speeds. To improve the conversion rate, both the analog (comparator array) and the digital (encoder) parts of the ADC are fully pipelined. Furthermore, the logic functions in the encoder are reformulated to reduce wire crossings and delay and to equalize the wires lengths in the layout. To keep the design simple, inductors are avoided. As a result, a compact design with small wire parasitics is achieved. Moreover, some geometric layout techniques, including a common centroid layout for the resistor ladder, are introduced to reduce the effect of mismatches to eliminate the use of digital calibration. The ADC is designed and fabricated in 0.18um CMOS and operates at 4GS/s. It achieves an effective number of bits (ENOB) of 3.71 (3.14, 2.75) for a 10MHz (0.501GHz, 1.491GHz) signal sampled at 4GS/s (3GS/s, 3GS/s). Differential/integral nonlinearity (DNL/INL) errors are between +/-0.35LSB and +/-0.26LSB, respectively. The ADC consumes 43mW from a 1.8V supply and occupies 0.06mm2 active area. Due to the use of CML circuits, the ADC achieves the highest speed reported for a single channel 4 bit ADC in a 0.18um CMOS technology. It also reports the best power performance among the 4-bit ADCs with similar or higher speeds. The active area is also among the smallest reported. In addition, in this thesis, the signal to noise ratio (SNR) of an ADC is formulated in terms of its INL performance. The related formulas in the literature are not accurate for low resolution ADCs, and yet they do not take the input waveform into account. Two standard waveforms, ramp and sinusoid, are considered here. The SNR formulas are derived and confirmed by simulation results.

Flash Analog-to-Digital Converters (ADCs), targeting optical communication standards, have been reported in SiGe BiCMOS technology. CMOS implementation of such designs faces two challenges. The first is to achieve a high sampling speed, given the lower gain-bandwidth (lower ft) of CMOS technology. The second challenge is to handle the wide bandwidth of the input signal with a certain accuracy. Although the first problem can be relaxed by using the time-interleaved architecture, the second problem remains as a main obstacle to CMOS implementation. As a result, the feasibility of the CMOS implementation of ADCs for such applications, or other wide band applications, depends primarily on achieving a very small input capacitance (large bandwidth) at the desired accuracy. In the flash architecture, the input capacitance is traded off for the achievable accuracy. This tradeoff becomes tighter with technology scaling. An effective way to ease this tradeoff is to use resistive offset averaging. This permits the use of smaller area transistors, leading to a reduction in the ADC input capacitance. In addition, interpolation can be used to decrease the input capacitance of flash ADCs. In an interpolating architecture, the number of ADC input preamplifiers is reduced significantly, and a resistor network interpolates the missing zero-crossings needed for an N-bit conversion. The resistive network also averages out the preamplifiers offsets. Consequently, an interpolating network works also as an averaging network. The resistor network used for averaging or interpolation causes a systematic non-linearity at the ADC transfer characteristics edges. The common solution to this problem is to extend the preamplifiers array beyond the input signal voltage range by using dummy preamplifiers. However, this demands a corresponding extension of the flash ADC reference-voltage resistor ladder. Since the voltage headroom of the reference ladder is considered to be a main bottleneck in the implementation of flash ADCs in deep-submicron technologies with reduced supply voltage, extending the reference voltage beyond the input voltage range is highly undesirable. The principal objective of this thesis is to develop a new circuit technique to enhance the bandwidth-accuracy product of flash ADCs. Thus, first, a rigorous analysis of flash ADC architectures accuracy-bandwidth tradeoff is presented. It is demonstrated that the interpolating architecture achieves a superior accuracy compared to that of a full flash architecture for the same input capacitance, and hence would lead to a higher bandwidth-accuracy product, especially in deep-submicron technologies that use low power supplies. Also, the gain obtained, when interpolation is employed, is quantified. In addition, the limitations of a previous claim, which suggests that an interpolating architecture is equivalent to an averaging full flash architecture that trades off accuracy for the input capacitance, is presented. Secondly, a termination technique for the averaging/interpolation network of flash ADC preamplifiers is devised. The proposed technique maintains the linearity of the ADC at the transfer characteristics edges and cancels out the over-range voltage, consumed by the dummy preamplifiers. This makes flash ADCs more amenable for integration in deep-submicron CMOS technologies. In addition, the elimination of this over-range voltage allows a larger least-significant bit. As a result, a higher input referred offset is tolerated, and a significant reductions in the ADC input capacitance and power dissipation are achieved at the same accuracy. Unlike a previous solution, the proposed technique does not introduce negative transconductance at flash ADC preamplifiers array edges. As a result, the offset averaging technique can be used efficiently. To prove the resulting saving in the ADC input capacitance and power dissipation that is attained by the proposed termination technique, a 6-bit 1.6-GS/s flash ADC test chip is designed and implemented in 0.13-$\mu$m CMOS technology. The ADC consumes 180 mW from a 1.5-V supply and achieves a Signal-to-Noise-plus-Distortion Ratio (SNDR) of 34.5 dB and 30 dB at 50-MHz and 1450-MHz input signal frequency, respectively. The measured peak Integral-Non-Linearity (INL) and Differential-Non-Linearity (DNL) are 0.42 LSB and 0.49 LSB, respectively.

Flash Analog-to-Digital Converters (ADCs), targeting optical communication standards, have been reported in SiGe BiCMOS technology. CMOS implementation of such designs faces two challenges. The first is to achieve a high sampling speed, given the lower gain-bandwidth (lower ft) of CMOS technology. The second challenge is to handle the wide bandwidth of the input signal with a certain accuracy. Although the first problem can be relaxed by using the time-interleaved architecture, the second problem remains as a main obstacle to CMOS implementation. As a result, the feasibility of the CMOS implementation of ADCs for such applications, or other wide band applications, depends primarily on achieving a very small input capacitance (large bandwidth) at the desired accuracy. In the flash architecture, the input capacitance is traded off for the achievable accuracy. This tradeoff becomes tighter with technology scaling. An effective way to ease this tradeoff is to use resistive offset averaging. This permits the use of smaller area transistors, leading to a reduction in the ADC input capacitance. In addition, interpolation can be used to decrease the input capacitance of flash ADCs. In an interpolating architecture, the number of ADC input preamplifiers is reduced significantly, and a resistor network interpolates the missing zero-crossings needed for an N-bit conversion. The resistive network also averages out the preamplifiers offsets. Consequently, an interpolating network works also as an averaging network. The resistor network used for averaging or interpolation causes a systematic non-linearity at the ADC transfer characteristics edges. The common solution to this problem is to extend the preamplifiers array beyond the input signal voltage range by using dummy preamplifiers. However, this demands a corresponding extension of the flash ADC reference-voltage resistor ladder. Since the voltage headroom of the reference ladder is considered to be a main bottleneck in the implementation of flash ADCs in deep-submicron technologies with reduced supply voltage, extending the reference voltage beyond the input voltage range is highly undesirable. The principal objective of this thesis is to develop a new circuit technique to enhance the bandwidth-accuracy product of flash ADCs. Thus, first, a rigorous analysis of flash ADC architectures accuracy-bandwidth tradeoff is presented. It is demonstrated that the interpolating architecture achieves a superior accuracy compared to that of a full flash architecture for the same input capacitance, and hence would lead to a higher bandwidth-accuracy product, especially in deep-submicron technologies that use low power supplies. Also, the gain obtained, when interpolation is employed, is quantified. In addition, the limitations of a previous claim, which suggests that an interpolating architecture is equivalent to an averaging full flash architecture that trades off accuracy for the input capacitance, is presented. Secondly, a termination technique for the averaging/interpolation network of flash ADC preamplifiers is devised. The proposed technique maintains the linearity of the ADC at the transfer characteristics edges and cancels out the over-range voltage, consumed by the dummy preamplifiers. This makes flash ADCs more amenable for integration in deep-submicron CMOS technologies. In addition, the elimination of this over-range voltage allows a larger least-significant bit. As a result, a higher input referred offset is tolerated, and a significant reductions in the ADC input capacitance and power dissipation are achieved at the same accuracy. Unlike a previous solution, the proposed technique does not introduce negative transconductance at flash ADC preamplifiers array edges. As a result, the offset averaging technique can be used efficiently. To prove the resulting saving in the ADC input capacitance and power dissipation that is attained by the proposed termination technique, a 6-bit 1.6-GS/s flash ADC test chip is designed and implemented in 0.13-$\mu$m CMOS technology. The ADC consumes 180 mW from a 1.5-V supply and achieves a Signal-to-Noise-plus-Distortion Ratio (SNDR) of 34.5 dB and 30 dB at 50-MHz and 1450-MHz input signal frequency, respectively. The measured peak Integral-Non-Linearity (INL) and Differential-Non-Linearity (DNL) are 0.42 LSB and 0.49 LSB, respectively.

Thesis (M.Phil.)--Hong Kong University of Science and Technology, 2003. / Includes bibliographical references. Also available in electronic version. Access restricted to campus users.

Includes bibliographical references (p. 118-120).