The College of Engineering at the University of Central Florida has a flight simulator. This simulator was built as a stand-alone Instrument Flight Rules (IFR) training aid. The college has attempted on several occasions to augment this simulator system with a visual (out the cockpit view) simulation for the trainee pilot. Funding and resources have restricted or limited these enhancements to non real-time simulation. This project/thesis provides the university with part of the solution to accurate real time simulation. The simulated aircraft position and direction is acquired at 9 to 40 Hertz with 10-bit resolution. This data is made available in the ubiquitous RS-232C standard format. Thus any size computer can utilize the position and direction information for the simulated aircraft. With this element completed, a future project can utilize this information for time and motion studies or visual simulation.

Delta-sigma analog-to-digital converters traditionally have been used for low speed, high resolution applications such as measurements, sensors, voice and audio systems. Through continued device scaling in CMOS technology and architectural and circuit level design innovations, they have even become popular for wideband, high dynamic range applications such as wired and wireless communication systems. Therefore, power efficient wideband low power delta-sigma data converters that bridges analog and digital have become mandatory for popular mobile applications today. In this dissertation, two architectural innovations and a development and realization of a state-of-the-art delta-sigma analog to digital converter with effective design techniques in both architectural and circuit levels are presented. The first one is timing-relaxed double noise coupling which effectively provides 2nd order noise shaping in the noise transfer function and overcomes stringent timing requirement for quantization and DEM. The second one presented is a noise shaping SAR quantizer, which provides one order of noise shaping in the noise transfer function. It uses a charge redistribution SAR quantizer and is applied to a timing-relaxed lowdistortion delta-sigma modulator which is suitable for adopting SAR quantizer. Finally a cascade switched capacitor delta-sigma analog-to-digital converter suitable for WLAN applications is presented. It uses a noise folding free double sampling technique and an improved low-distortion architecture with an embedded-adder integrator. The prototype chip is fabricated with a double poly, 4 metal, 0.18μm CMOS process. The measurement result achieves 73.8 dB SNDR over 10 MHz bandwidth. The figure of merit defined by FoM = P/(2 x BW x 2[superscript ENOB]) is 0.27 pJ/conv-step. The measurement results indicate that the proposed design ideas are effective and useful for wideband, low power delta-sigma analog-to-digital converters with low oversampling ratio. / Graduation date: 2012 / Access restricted to the OSU Community at author's request from June 19, 2012 - June 19, 2013

Most present day implementations of delta-sigma modulators are discrete-time ones using switched-capacitor circuits. A resistor-capacitor (RC) implementation of a delta-sigma analog to digital converter (ADC) does not use switched capacitor (SC) technology. While SC implementation has the advantages of being discrete-time, no resistors used and improved stability control, RC implementation has the advantage of no switches being used (other than quantizer) and therefore a simpler circuit implementation. Continuous-time implementations can achieve lower thermal noise levels than switched capacitor modulators. Butterworth Multi-stage Noise Shaping (MASH) architecture is one of the promising architectures to implement in continuous-time domain. For a convenient design and quantization noise spectrum shaping of a delta sigma data converter, it's highly desirable for the Noise Transfer Function (NTF) to take the form of a high-pass filter. The MASH architecture was introduced to overcome stability problems commonly faced beyond a second order structure. Delta-sigma data converters are new converter designs that are preferred for integrated circuits and for high-resolution applications. It is highly desirable for the NTF of delta-sigma data converters to take the form of conventional highpass filters for convenient design purposes and shaping of the quantization noise spectrum. However, conventional delta-sigma architectures allow for only low orders and very low cutoff frequencies for such highpass filters, otherwise the converter becomes unstable. In previous projects it was found that a MASH implementation (each stage being second order) of a delta-sigma data converter where the NTF of each stage is a Butterworth highpass filter holds much promise. This current project is to accomplish RC implementation of fourth-order Butterworth MASH delta-sigma data converter. The circuit design procedure will be shown, starting with the desired NTF characteristics, and yielding the required parameters for the RC integrators with gains that are determined from the desired transfer function. The circuit simulation, yielding the bit stream frequency spectrum and the signal to noise ratio, will be based on Mentor Graphics Eldo SPICE simulations. The performance and characteristics of the circuit is fully analyzed and documented for a wide variety of variations and test conditions. / Thesis (M.S.)--Wichita State University, College of Engineering, Dept. of Electrical and Computer Engineering. / "August 2006." / Includes bibliographic references (leaves 41-43).

Delta sigma data converters have found to be of greater interest for almost 40 years now. Continuous time implementation of these converters, especially for high speed and low power applications has been very challenging. Here in this thesis we have discussed Resistor Capacitor (RC) implementation of Chebyshev Type II high pass Noise Transfer Function (NTF). RC implementation has its own advantages compared to that of a Switched Capacitor (SC) circuit. While SC implementation has the advantages of being discrete-time, no resistors used, and improved stability control, RC implementation has the advantage of no switches being used (other than the quantizer) and therefore a simpler circuit implementation. In this thesis the details of the design and analysis of a fourth order RC delta sigma data converter will be given. The NTF is that of a fourth-order Chebyshev Type II highpass filter, where the noise is high passed and removed using a low pass filter and the signal remains constant across the low frequency band. The circuit implementation consists of four RC integrators with gain stages that are determined from the desired transfer function. The feedback loop includes of a sample and hold circuit followed by a one-bit quantizer: these are the only nonlinear elements in the circuit design. The circuit design procedure will be given, starting with the desired NTF characteristics, and yielding the required gain parameters for the four integrator circuit architecture, obtained to implement the requiredH(s). MATLAB is used for easy computation. The circuit simulation, yielding the bit stream frequency spectrum and the signal to noise ratio, will be based on Mentor Graphics Eldo SPICE simulations. The overall performance achieves the equivalent of 11 bits. This is obtained from a fourth order circuit, using RC implementation. / Thesis (M.S.)--Wichita State University, College of Engineering, Dept. of Electrical and Computer Engineering. / Includes bibliographical references (leaves 37-38) / "December 2006."

Thesis (Ph. D.)--University of Washington, 2007. / Vita. Includes bibliographical references (leaves 102-106).

Thesis (Ph. D.)--University of Washington, 2006. / Vita. Includes bibliographical references (p. 111-117).

No description available.

Call number: LD2668 .T4 1984 R33 / Master of Science

A photonic analog-to-digital converter (ADC) based on a robust symmetrical number system (RSNS) was constructed and tested. The analog signal to be converted is used to amplitude modulate an optical pulse from a laser using three Mach-Zehnder interferometers (MZI). The Mach-Zehnder interferometers fold the input analog signal for a three-channel RSNS encoding. The folding waveforms are then detected and amplitude-analyzed by three separate comparator banks, the outputs of which are used to determine a digital representation of the analog signal. This design uses the RSNS preprocessing to encode the signal with the fewest number of comparators for any selected bit resolution. In addition to the efficiency of its use of comparators, the RSNS encoding has inherent Gray-code properties making it particularly attractive for eliminating any possible encoding errors. The RSNS encoding is combined with an optical infrastructure that offers high bandwidth and low insertion loss characteristics. A full implementation was constructed and tested. The lack of a high-speed data acquisition device limited the results to examining the preprocessing and digital processing separately. With the system integration of a data acquisition device, a wideband direct digital antenna architecture can be demonstrated.

Typescript (photocopy). / Digitized by Kansas State University Libraries