Actuellement, nous vivons dans une société numérique. L'avènement de l'Internet et l'arrivée du multimédia et des supports de stockage numériques, ont transformé profondément la façon dont nous communiquons. L'image en particulier occupe une place très importante dans la communication interpersonnelle moderne. Toutefois, elle présente l'inconvénient d'être représentée par une quantité d'information très importante. De ce fait, la transmission et le stockage des images soulèvent certains problèmes qui sont liés essentiellement à la sécurité et à la compression d'images. Ce sont ces considérations qui ont guidé cette thèse. En effet, la problématique que nous posons dans cette thèse est de proposer une solution conduisant à la crypto-compression d'images afin d'assurer un archivage et un transfert sécurisés tout en conservant les performances de la méthode de compression utilisée. En effet, nos travaux de recherche ont porté essentiellement sur la compression et le cryptage des images numériques. Concernant la compression, nous avons porté un intérêt particulier au codage arithmétique vu sont efficacité en terme de ta ux de compression et son utilisation par les nouvelles normes et standards de compression tel que JPEG2000, JBIG, JBIG2 et H.264/AVC. Quant au cryptage, nous avons opté pour l'utilisation du chaos combiné avec les fractions continues afin de générer des flux de clés ayant à la fois de bonnes propriétés cryptographiques et statistiques. Ainsi, nous avons proposé deux nouvelles méthodes de compression sans perte basées sur le codage arithmétique tout en introduisant de nouveaux paramètres de codage afin de réduire davantage la taille en bits des images compressées. Deux autres méthodes s'appuient sur l'utilisation du chaos et des fractions continues pour le développement d'un générateur de nombres pseudo-aléatoires et le cryptage par flot d'images. Enfin, nous proposons une nouvelle méthode qui emploie conjointement le cryptage avec la compression. Cette dernière méthode se base sur l'échange des sous-intervalles associés aux symboles d'un codeur arit hmétique binaire de façon aléatoire tout en exploitant notre générateur de nombres pseudo-aléatoire. Elle est efficace, sécurisée et conserve le taux de compression obtenu par le codage arithmétique et ceci quelque soit le modèle statistique employé : statique ou adaptatif. / Actually, we live in a digital society. The proliferation of the Internet and the rapid progress in information technology on multimedia, have profoundly transformed the way we communicate. An enormous amount of media can be easily exchanged through the Internet and other communication networks. Digital image in particular occupies an important place in modern interpersonal communication. However, image data have special features such as bulk capacity. Thus, image security and compression issues have became exceptionally acute. It is these considerations that have guided this thesis. Thus, we propose throw this thesis to incorporating security requirements in the data compression system to ensure reasonable security without downgrading the compression performance.For lossless image compression, we have paid most attention to the arithmetic coding (AC) which has been widely used as an efficient compression algorithm in the new standards including JBIG, JBIG2, JPEG2000 and H.264/AVC. For image encryption, we are based on the combination of a chaotic system and the Engel continued fraction map to generate key-stream with both good chaotic and statistical properties. First, we have proposed two new schemes for lossless image compression based on adding new pre-treatment steps and on proposing new modeling methods to estimate probabilities for AC. Experimental results demonstrate that the proposed schemes give mean compression ratios that are significantly higher than those by the conventional AC. In addition, we have proposed a new pseudo-random bit generator (PRBG). The detailed analysis done by NIST statistical test Suite demonstrates that the proposed PRGB is suitable for cryptography. The proposed PRBG is used to develop a new symmetr ic stream cipher for image encryption. Theoretic and numerical simulation analyses indicate that our image encryption algorithm is efficient and satisfies high security. Finally, we have proposed a new scheme which performs both lossless compression and encryption of image. The lossless compression is based on the binary AC (BAC) and the encryption is based on the proposed PRBG. The numerical simulation analysis indicates that the proposed compression and encryption scheme satisfies highly security with no loss of the BAC compression efficiency.

The aim of this dissertation is to develop a new algorithm to embed a watermark in JPEG compressed images, using encoding methods. This encompasses the embedding of proprietary information, such as identity and authentication bitstrings, into the compressed material. This watermark encoding scheme involves combining entropy coding with homophonic coding, in order to embed a watermark in a JPEG image. Arithmetic coding was used as the entropy encoder for this scheme. It is often desired to obtain a robust digital watermarking method that does not distort the digital image, even if this implies that the image is slightly expanded in size before final compression. In this dissertation an algorithm that combines homophonic and arithmetic coding for JPEG images was developed and implemented in software. A detailed analysis of this algorithm is given and the compression (in number of bits) obtained when using the newly developed algorithm (homophonic and arithmetic coding). This research shows that homophonic coding can be used to embed a watermark in a JPEG image by using the watermark information for the selection of the homophones. The proposed algorithm can thus be viewed as a ‘key-less’ encryption technique, where an external bitstring is used as a ‘key’ and is embedded intrinsically into the message stream. The algorithm has achieved to create JPEG images with minimal distortion, with Peak Signal to Noise Ratios (PSNR) of above 35dB. The resulting increase in the entropy of the file is within the expected 2 bits per symbol. This research endeavor consequently provides a unique watermarking technique for images compressed using the JPEG standard. / Dissertation (MEng)--University of Pretoria, 2008. / Electrical, Electronic and Computer Engineering / unrestricted

<p>To achieve greater compression ratios new video and image CODECs like H.264 and JPEG 2000 take advantage of Context adaptive binary arithmetic coding. As it contains computationally heavy algorithms, fast implementations have to be made when they are performed on large amount of data such as compressing high resolution formats like HDTV. This document describes how entropy coding works in general with a focus on arithmetic coding and CABAC. Furthermore the document dicusses the demands of the different CABACs and propose different options to hardware and instruction level optimisation. Testing and benchmarking of these implementations are done to ease evaluation. The main contribution of the thesis is parallelising and unifying the CABACs which is discussed and partly implemented. The result of the ILA is improved program flow through a specialised branching operations. The result of the DHA is a two bit parallel accelerator with hardware sharing between JPEG 2000 and H.264 encoder with limited decoding support.</p>

Advances in electronics, computer and information technology are fueling major changes in the area of power systems instrumentations. More and more microprocessor based digital instruments are replacing older type of meters. Extensive deployment of digital instruments are generating vast quantities of data which is creating information pressure in Utilities. The legacy SCADA based data management systems do not support management of such huge data. As a result utilities either have to delete or store the metered information in some compact discs, tape drives which are unreliable. Also, at the same time the traditional integrated power industry is going through a deregulation process. The market principle is forcing competition between power utilities, which in turn demands a higher focus on profit and competitive edge. To optimize system operation and planning utilities need better decision making processes which depend on the availability of reliable system information. For utilities it is becoming clear that information is a vital asset. So, the utilities are now keen to store and use as much information as they can. Existing SCADA based systems do not allow to store data of more than a few months. So, in this dissertation effectiveness of compression algorithms in compressing real time operational data has been assessed. Both, lossy and lossless compression schemes are considered. In lossless method two schemes are proposed among which Scheme 1 is based on arithmetic coding and Scheme 2 is based on run length coding. Both the scheme have 2 stages. First stage is common for both the schemes. In this stage the consecutive data elements are decorrelated by using linear predictors. The output from linear predictor, named as residual sequence, is coded by arithmetic coding in Scheme 1 and by run length coding in Scheme 2. Three different types of arithmetic codings are considered in this study : static, decrement and adaptive arithmetic coding. Among them static and decrement codings are two pass methods where the first pass is used to collect symbol statistics while the second is used to code the symbols. The adaptive coding method uses only one pass. In the arithmetic coding based schemes the average compression ratio achieved for voltage data is around 30, for frequency data is around 9, for VAr generation data is around 14, for MW generation data is around 11 and for line flow data is around 14. In scheme 2 Golomb-Rice coding is used for compressing run lengths. In Scheme 2 the average compression ratio achieved for voltage data is around 25, for frequency data is around 7, for VAr generation data is around 10, for MW generation data is around 8 and for line flow data is around 9. The arithmetic coding based method mainly looks at achieving high compression ratio. On the other hand, Golomb-Rice coding based method does not achieve good compression ratio as arithmetic coding but it is computationally very simple in comparison with the arithmetic coding. In lossy method principal component analysis (PCA) based compression method is used. From the data set, a few uncorrelated variables are derived and stored. The range of compression ratio in PCA based compression scheme is around 105-115 for voltage data, around 55-58 for VAr generation data, around 21-23 for MW generation data and around 27-29 for line flow data. This shows that the voltage parameter is amenable for better compression than other parameters. Data of five system parameters - voltage, line flow, frequency, MW generation and MVAr generation - of Souther regional grid of India have been considered for study. One of the aims of this thesis is to argue that collected power system data can be put to other uses as well. In particular we show that, even mining the small amount of practical data (collected from SRLDC) reveals some interesting system behavior patterns. A noteworthy feature of the thesis is that all the studies have been carried out considering data of practical systems. It is believed that the thesis opens up new questions for further investigations.

O codificador aritmético binário adaptativo ao contexto adotado (CABAC – Context-based Adaptive Binary Arithmetic Coding) pelo padrão H.264/AVC a partir de perfil Main é o estado-da-arte em termos de eficiência de taxa de bits. Entretanto, o CABAC ocupa 9.6% do tempo total de processamento e seu throughput é limitado pelas dependências de dados no nível de bit (LIN, 2010). Logo, atingir os requisitos de desempenho em tempo real nos níveis mais altos do padrão H.264/AVC se torna uma tarefa árdua em software, sendo necesário então, a aceleração do CABAC através de implementações em hardware. As arquiteturas de hardware encontradas na literatura para o CABAC focam no Codificador Aritmético Binário (BAE - Binary Arithmetic Encoder) enquanto que a Binarização e Modelagem de Contextos (BCM – Binarization and Context Modeling) fica em segundo plano ou nem é apresentada. O BCM e o BAE juntos constituem o CABAC. Esta dissertação descreve detalhadamente o conjunto de algoritmos que compõem o BCM do padrão H.264/AVC. Em seguida, o projeto de uma arquitetura de hardware específica para o BCM é apresentada. A solução proposta é descrita em VHDL e os resultados de síntese mostram que a arquitetura alcança desempenho suficiente, em FPGA e ASIC, para processar vídeos no nível 5 do padrão H.264/AVC. A arquitetura proposta é 13,3% mais rápida e igualmente eficiente em área que os melhores trabalhos relacionados nestes quesitos. / Context-based Adaptive Binary Arithmetic Coding (CABAC) adopted in the H.264/AVC main profile is the state-of-art in terms of bit-rate efficiency. However, CABAC takes 9.6% of the total encoding time and its throughput is limited by bit-level data dependency (LIN, 2010). Moreover, meeting real-time requirement for a pure software CABAC encoder is difficult at the highest levels of the H.264/AVC standard. Hence, speeding up the CABAC by hardware implementation is required. The CABAC hardware architectures found in the literature focus on the Binary Arithmetic Encoder (BAE), while the Binarization and Context Modeling (BCM) is a secondary issue or even absent in the literature. Integrated, the BCM and the BAE constitute the CABAC. This dissertation presents the set of algorithms that describe the BCM of the H.264/AVC standard. Then, a novel hardware architecture design for the BCM is presented. The proposed design is described in VHDL and the synthesis results show that the proposed architecture reaches sufficiently high performance in FPGA and ASIC to process videos in real-time at the level 5 of H.264/AVC standard. The proposed design is 13.3% faster than the best works in these items, while being equally efficient in area.

O codificador aritmético binário adaptativo ao contexto adotado (CABAC – Context-based Adaptive Binary Arithmetic Coding) pelo padrão H.264/AVC a partir de perfil Main é o estado-da-arte em termos de eficiência de taxa de bits. Entretanto, o CABAC ocupa 9.6% do tempo total de processamento e seu throughput é limitado pelas dependências de dados no nível de bit (LIN, 2010). Logo, atingir os requisitos de desempenho em tempo real nos níveis mais altos do padrão H.264/AVC se torna uma tarefa árdua em software, sendo necesário então, a aceleração do CABAC através de implementações em hardware. As arquiteturas de hardware encontradas na literatura para o CABAC focam no Codificador Aritmético Binário (BAE - Binary Arithmetic Encoder) enquanto que a Binarização e Modelagem de Contextos (BCM – Binarization and Context Modeling) fica em segundo plano ou nem é apresentada. O BCM e o BAE juntos constituem o CABAC. Esta dissertação descreve detalhadamente o conjunto de algoritmos que compõem o BCM do padrão H.264/AVC. Em seguida, o projeto de uma arquitetura de hardware específica para o BCM é apresentada. A solução proposta é descrita em VHDL e os resultados de síntese mostram que a arquitetura alcança desempenho suficiente, em FPGA e ASIC, para processar vídeos no nível 5 do padrão H.264/AVC. A arquitetura proposta é 13,3% mais rápida e igualmente eficiente em área que os melhores trabalhos relacionados nestes quesitos. / Context-based Adaptive Binary Arithmetic Coding (CABAC) adopted in the H.264/AVC main profile is the state-of-art in terms of bit-rate efficiency. However, CABAC takes 9.6% of the total encoding time and its throughput is limited by bit-level data dependency (LIN, 2010). Moreover, meeting real-time requirement for a pure software CABAC encoder is difficult at the highest levels of the H.264/AVC standard. Hence, speeding up the CABAC by hardware implementation is required. The CABAC hardware architectures found in the literature focus on the Binary Arithmetic Encoder (BAE), while the Binarization and Context Modeling (BCM) is a secondary issue or even absent in the literature. Integrated, the BCM and the BAE constitute the CABAC. This dissertation presents the set of algorithms that describe the BCM of the H.264/AVC standard. Then, a novel hardware architecture design for the BCM is presented. The proposed design is described in VHDL and the synthesis results show that the proposed architecture reaches sufficiently high performance in FPGA and ASIC to process videos in real-time at the level 5 of H.264/AVC standard. The proposed design is 13.3% faster than the best works in these items, while being equally efficient in area.

To achieve greater compression ratios new video and image CODECs like H.264 and JPEG 2000 take advantage of Context adaptive binary arithmetic coding. As it contains computationally heavy algorithms, fast implementations have to be made when they are performed on large amount of data such as compressing high resolution formats like HDTV. This document describes how entropy coding works in general with a focus on arithmetic coding and CABAC. Furthermore the document dicusses the demands of the different CABACs and propose different options to hardware and instruction level optimisation. Testing and benchmarking of these implementations are done to ease evaluation. The main contribution of the thesis is parallelising and unifying the CABACs which is discussed and partly implemented. The result of the ILA is improved program flow through a specialised branching operations. The result of the DHA is a two bit parallel accelerator with hardware sharing between JPEG 2000 and H.264 encoder with limited decoding support.

O codificador aritmético binário adaptativo ao contexto adotado (CABAC – Context-based Adaptive Binary Arithmetic Coding) pelo padrão H.264/AVC a partir de perfil Main é o estado-da-arte em termos de eficiência de taxa de bits. Entretanto, o CABAC ocupa 9.6% do tempo total de processamento e seu throughput é limitado pelas dependências de dados no nível de bit (LIN, 2010). Logo, atingir os requisitos de desempenho em tempo real nos níveis mais altos do padrão H.264/AVC se torna uma tarefa árdua em software, sendo necesário então, a aceleração do CABAC através de implementações em hardware. As arquiteturas de hardware encontradas na literatura para o CABAC focam no Codificador Aritmético Binário (BAE - Binary Arithmetic Encoder) enquanto que a Binarização e Modelagem de Contextos (BCM – Binarization and Context Modeling) fica em segundo plano ou nem é apresentada. O BCM e o BAE juntos constituem o CABAC. Esta dissertação descreve detalhadamente o conjunto de algoritmos que compõem o BCM do padrão H.264/AVC. Em seguida, o projeto de uma arquitetura de hardware específica para o BCM é apresentada. A solução proposta é descrita em VHDL e os resultados de síntese mostram que a arquitetura alcança desempenho suficiente, em FPGA e ASIC, para processar vídeos no nível 5 do padrão H.264/AVC. A arquitetura proposta é 13,3% mais rápida e igualmente eficiente em área que os melhores trabalhos relacionados nestes quesitos. / Context-based Adaptive Binary Arithmetic Coding (CABAC) adopted in the H.264/AVC main profile is the state-of-art in terms of bit-rate efficiency. However, CABAC takes 9.6% of the total encoding time and its throughput is limited by bit-level data dependency (LIN, 2010). Moreover, meeting real-time requirement for a pure software CABAC encoder is difficult at the highest levels of the H.264/AVC standard. Hence, speeding up the CABAC by hardware implementation is required. The CABAC hardware architectures found in the literature focus on the Binary Arithmetic Encoder (BAE), while the Binarization and Context Modeling (BCM) is a secondary issue or even absent in the literature. Integrated, the BCM and the BAE constitute the CABAC. This dissertation presents the set of algorithms that describe the BCM of the H.264/AVC standard. Then, a novel hardware architecture design for the BCM is presented. The proposed design is described in VHDL and the synthesis results show that the proposed architecture reaches sufficiently high performance in FPGA and ASIC to process videos in real-time at the level 5 of H.264/AVC standard. The proposed design is 13.3% faster than the best works in these items, while being equally efficient in area.

This work deals with image compression using wavelet transformation. At the beginning , you can find theoretical information about the best known techniques used for image compression , a thorough description of wavelet transormation and the EBCOT algorithm. A significant part of the work is devoted to the library's own implementation . Another chapter of the diploma thesis deals with the comparison and evaluation of the achieved results of the processed library with the JPEG2000 format

Purpose of this thesis is to describe the context-based compression methods and their application to multimedia data. There is described the principle of arithmetic coding and prediction by partial matching method, including creation of the probability model. There are also described multimedia data and the basic principles of their compression. The next section presents compression methods, that I implemented at work and their results.