The ideal memory system assumed by most programmers is one which has high capacity, yet allows any word to be accessed instantaneously. To make the hardware approximate this performance, an increasingly complex memory hierarchy, using caches and techniques like automatic prefetch, has evolved. However, as the gap between processor and memory speeds continues to widen, these programmer-visible mechanisms are becoming inadequate. Part of the recent increase in processor performance has been due to the introduction of programmer/compiler-visible SWAR (SIMD Within A Register) parallel processing on increasingly wide DATA LARs (Line Associative Registers) as a way to both improve data access speed and increase efficiency of SWAR processing. Although the base concept of DATA LARs predates this thesis, this thesis presents the first instruction set architecture specification complete enough to allow construction of a detailed prototype hardware design. This design was implemented and tested using a hardware simulator.

As technological advances have improved processor speed, main memory speed has lagged behind. Even with advanced RAM technologies, it has not been possible to close the gap in speeds. Ideally, a CPU can deliver good performance when the right data is made available to it at the right time. Caches and Registers solved the problem to an extent. This thesis takes the approach of trying to create a new memory access model that is more efficient and simple instead of using various add on mechanisms to mask high memory latency. The Line Associative Registers have the functionality of a cache, scalar registers and vector registers built into them. This new model qualitatively changes how the processor accesses memory.

Effective production scheduling is essential for improved performance. Scheduling strategies for various shop configurations and performance criteria have been widely studied. Scheduling in parallel machines (PM) is one among the many scheduling problems that has received considerable attention in the literature. An even more complex scheduling problem arises when there are several PM families and jobs are capable of being processed in more than one such family. This research addresses such a situation, which is defined as an Associative Parallel Machine scheduling (APMS) problem. This research presents the SAPT-II algorithm that solves a highly constrained APMS problem with the objective to minimize average flow time. A case example from a make-to-order industrial product manufacturer is used to illustrate the complexity of the problem and evaluate the effectiveness of the scheduling algorithm.

Modern processor architectures suffer from an ever increasing gap between processor and memory performance. The current memory-register model attempts to hide this gap by a system of cache memory. Line Associative Registers(LARs) are proposed as a new system to avoid the memory gap by pre-fetching and associative updating of both instructions and data. This thesis presents a fully LAR-based architecture, targeting a previously developed instruction set architecture. This architecture features an execution pipeline supporting SWAR operations, and a memory system supporting the associative behavior of LARs and lazy writeback to memory.

No description available.

Retrospective revaluation— learning about implied but unpresented cues— poses one of the greatest challenges to classical learning theories. Whereas theorists have revised their models to accommodate revaluation, the empirical reliability of the phenomenon remains contentious. I present two sets of experiments that examine revaluative learning under different but analogous experimental protocols. Results provided mixed empirical evidence that is difficult to interpret in isolation. To address the issue, I apply two computational models to the experiments. An instance-based model of associative learning (Jamieson et al., 2012) predicts retrospective revaluation and anticipates participant behaviour in one set of experiments. An updated classical learning model (Ghirlanda, 2005) fails to predict retrospective revaluation, but anticipates participant behaviour in the other set of experiments. I argue that retrospective revaluation emerges as a corollary of basic memorial processes and discuss the empirical and theoretical implications.

The present research sought to describe and explain age related changes to associative learning processes. Eleven experiments were conducted using a human conditional learning paradigm. Background data on health, lifestyle, and cognitive ability were collected and used as predictor variables in multiple regression analyses. Experiments 1 to 8 were formative, and found that older participants showed an overall age related decline in learning ability exacerbated by the number of stimuli and outcomes used, and the concurrent presentation of different problem types. Configural models of learning (e.g. Pearce, 1994, 2002) best predicted young participants’ learning whereas older people’s learning was more consistent with elemental models (e.g. Rescorla-Wagner, 1972), suggesting an age related change in generalisation processes. Those who learned problems better were also more likely to be able to articulate a rule that had helped them learn the problem. Age itself was the most predominant predictor of accuracy in these experiments. Experiments 9, 10, and 11 were multiple stage experiments that looked at the extent of pro- and retro-active interference in learning. Experiments 9 and 10 used easy and hard HCL problems to examine the role of rule induction in learning. Older participants who had learned initial discriminations better were more prone to pro-active interference in both experiments, the extent of which was predicted most reliably by fluid intelligence. Rule learning had a profound effect on participants’ predictions during the unreinforced test stage. In Experiment 9 (Easy-Hard) younger participants suffered from more retroactive interference than older people. This pattern was far less pronounced in Experiment 10, (Hard-Easy) suggesting that problem order affected the way participants generalised from rule-based knowledge. This observation is inexplicable by associative learning theories, and explanation may require a problem solving approach. Experiment 11 examined feature-based generalisation. Again older participants suffered more proactive and retroactive interference and elemental theories predicted their responses best, whereas younger participants responses were consistent with configural models of learning. In this instance, resistance to pro- and retro-active interference was predicted by fluid intelligence. Overall the research concluded that there is a demonstrable, complexity dependent change in associative learning processes in later life. It appears that humans have an increasing tendency to rely on elemental, rather than configural processes of generalisation in later life, and this leads to overgeneralisation between stimuli and an inability to resist pro- and retroactive interference in learning. This may be as a result of an inhibitory or source monitoring failure as a consequence of atrophy in the frontal lobes of the brain, although some of the learning deficits are explicable through mnemonic decline.

This thesis reports an investigation on the feasibility study of a searching mechanism using an APP suitable for an on-line bibliographic retrieval, operation, especially for retrospective searches. From the study of the searching methods used in the conventional systems it is seen that elaborate file- and data- structures are introduced to improve the response time of the system. These consequently lead to software and hardware redundancies. To mask these complexities of the system an expensive computer with higher capabilities and more powerful instruction set is commonly used. Thus the service of the systen becomes cost-ineffective. On the other hand the primitive operations of a searching mechanism, such as, association, domain selection, intersection and unions, are the intrinsic features of an associative parallel processor. Therefore it is important to establish the feasibility of an APP as a cost-effective searching mechanise. In this thesis a searching mechanism using an 'ON-THE-FLY' searching technique has been proposed. The parallel search unit uses a Byte-oriented VRL-APP for efficient character string processing. At the time of undertaking this work the specification for neither the retrieval systems nor the BO-VRL APP's were well established; hence a two-phase investigation was originated. In the Phase I of the work a bottom up approach was adopted to derive a formal and precise specification for the BO-VRL-APP. During the Phase II of the work a top-down approach was opted for the implementation of the searching mechanism. An experimental research vehicle has been developed to establish the feasibility of an APP as a cost-effective searching mechanism. Although rigorous proof of the feasibility has not been obtained, the thesis establishes that the APP is well suited for on-line bibligraphic information retrieval operations where substring searches including boolean selection and threshold weights are efficiently supported.

Neurocomputers offer a massively parallel computing paradigm by mimicking the human brain. Their efficient use in statistical information processing has been proposed to overcome critical bottlenecks with traditional computing schemes for applications such as image and speech processing, and associative memory. In neural networks information is generally represented by phase (e.g., oscillatory neural networks) or amplitude (e.g., cellular neural networks). Phase-based neurocomputing is constructed as a network of coupled oscillatory neurons that are connected via programmable phase elements. Representing each neuron circuit with one oscillatory device and implementing programmable phases among neighboring neurons, however, are not clearly feasible from circuits perspective if not impossible. In contrast to nascent oscillatory neurocomputing circuits, mature amplitude-based neural networks offer more efficient circuit solutions using simpler resistive networks where information is carried via voltage- and current-mode signals. Yet, such circuits have not been efficiently realized by CMOS alone due to the needs for an efficient summing mechanism for weighted neural signals and a digitally-controlled weighting element for representing couplings among artificial neurons. Large power consumption and high circuit complexity of such CMOS-based implementations have precluded adoption of amplitude-based neurocomputing circuits as well, and have led researchers to explore the use of emerging technologies for such circuits. Although they provide intriguing properties, previously proposed neurocomputing components based on emerging technologies have not offered a complete and practical solution to efficiently construct an entire system. In this thesis we explore the generalized problem of co-optimization of technology and architecture for such systems, and develop a recipe for device requirements and target capabilities. We describe four plausible technologies, each of which could potentially enable the implementation of an efficient and fully-functional neurocomputing system. We first investigate fully-digital neural network architectures that have been tried before using CMOS technology in which many large-size logic gates such as D flip-flops and look-up tables are required. Using a newly-proposed all-magnetic non-volatile logic family, mLogic, we demonstrate the efficacy of digitizing the oscillators and phase relationships for an oscillatory neural network by exploiting the inherent storage as well as enabling an all-digital cellular neural network hardware with simplified programmability. We perform system-level comparisons of mLogic and 32nm CMOS for both networks consisting of 60 neurons. Although digital implementations based on mLogic offer improvements over CMOS in terms of power and area, analog neurocomputing architectures seem to be more compatible with the greatest portion of emerging technologies and devices. For this purpose in this dissertation we explore several emerging technologies with unique device configurations and features such as mCell devices, ovenized aluminum nitride resonators, and tunable multi-gate graphene devices to efficiently enable two key components required for such analog networks – that is, summing function and weighting with compact D/A (digital-to-analog) conversion capability. We demonstrate novel ways to implement these functions and elaborate on our building blocks for artificial neurons and synapses using each technology. We verify the functionality of each proposed implementation using various image processing applications based on compact circuit simulation models for such post-CMOS devices. Finally, we design a proof-of-concept neurocomputing circuitry containing 20 neurons using 65nm CMOS technology that is based on the primitives that we define for our analog neurocomputing scheme. This allows us to fully recognize the inefficiencies of an all-CMOS implementation for such specific applications. We share our experimental results that are in agreement with circuit simulations for the same image processing applications based on proposed architectures using emerging technologies. Power and area comparisons demonstrate significant improvements for analog neurocomputing circuits when implemented using beyond- CMOS technologies, thereby promising huge opportunities for future energy-efficient computing.

Thesis (M.S.)--Rochester Institute of Technology, 2008. / Typescript. Includes bibliographical references (leaves 73-75).