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M.Ing. / The drive for smaller and higher density power supplies have been realised by advances in switching technologies, higher frequencies and smaller components. Along with the advances of higher switching frequencies, came a number of restrictive parasitic effects that were insignificant at lower frequencies (in use a few years ago). A problem that is becoming of increasing concern, as the frequencies increase, rise times decrease and current levels increase, is the reactance of the parasitic inductance in voltage fed converter. This inductance is responsible for a multitude of limitations and problems in high frequency converters, with the most important being unstable voltage supplies, large voltage spikes during switching (which leads to electromagnetic interference), and power transfer limitations. The main contributors of this parasitic inductance was found to be the inherent inductance of the conductors of the DC bus, the internal inductance of the capacitor elements used in the DC bus and the paralleling of these capacitor elements (capacitor bank). It was decided to investigate the cause of these identified inductances in an attempt at finding a means to reduce them, thereby improving the performance of the converter. This was accompanied by a search into prediction methods for the inductance and capacitance of the DC bus conductors. The ability to predict the inductance and capacitance inherent to the DC bus conductors, will allow for a large decrease in prototyping, and should give insight into the causes of these elements and how to manipulate them. This was done for the DC bus conductors, and led to insight into their inductance and capacitance origins. Means to reduce this inductance was found, along with the ability to predict the inductance and capacitance of a number of DC bus conductors. The last two identified parasitic inductance sources, the internal inductance of the capacitors and inductance of the capacitor bank, were then investigated. The cause of the inductance in the capacitor elements was discovered, along with the factors on which the capacitor elements are dependent. A great deal of the inductance, and its associated effects, can be avoided through proper capacitor selection and correct capacitor bank design. In order to bring this study in context with a practical scenario, the information previously obtained was incorporated in a full bridge voltage fed converter. The previous findings on inductance and capacitance held equally well when applied to a practical scenario. Additional means to reduce the effects of the parasitic inductances were discovered, and the inductance and capacitance prediction methods proved to be relatively accurate when applied to the DC bus conductors of a physical converter.

The bject of these was finding, if tramway transport had to be displaced by trolley bus transport in Teplice.Tramway transport was in Teplice over 60 years, this theses concerns with development with tram-lines, accidents and unrealized projects, which were financial and technical ambitious often.Technical and fiancial availability of tramway and trolley bus transport is compared in last part.

Esse trabalho relata uma tentativa de demonstrar que o estudo de um conjunto de informações provenientes das discussões sobre os caminhos da Geografia, nas últimas décadas, pode permitir a identificação de conceitos e processos úteis para análise de relações entre equipamentos de transporte urbano, o Estado, o espaço e a difusão de inovações em nossa Sociedade. Para isso, relatam-se resultados de uma reflexão sobre o papel do espaço, o espaço urbano, relações entre o Estado e o espaço, a difusão de inovações, relações entre transporte urbano e espaço, e a história resumida do transporte por trolebus no Brasil. Detalham-se a análise de dados sobre a operação de trolebus em cinco cidades, onde hoje (1994), se transporta passageiros com o ônibus elétrico no Brasil, resultados de análise da história do trolebus sob os conceitos resultantes da reflexão exposta e conclusões gerais que corroboram com a tese demonstrada. / This work reports a trial to demonstrate that the study of a set of information from discussions about the last decade Geography\'s way can allow the identification of concepts and useful processes to explain the relationships between urban transportation equipments and the State, the space and the innovation difusion process in our Society. For this some meditation results on the space\'s role, urban space, relationships between space and State or urban transportation and space, innovation diffusion, and the story of trolleybus in Brazil was related. The data analysis on operation of trolleys in five cities, where today (1994) passengers are conducted by eletric buses in Brazil and the results of the trolley story on the concepts results from the reflexion exposed and the general conclusion that cooperate with this thesis are detailed here.

Esse trabalho relata uma tentativa de demonstrar que o estudo de um conjunto de informações provenientes das discussões sobre os caminhos da Geografia, nas últimas décadas, pode permitir a identificação de conceitos e processos úteis para análise de relações entre equipamentos de transporte urbano, o Estado, o espaço e a difusão de inovações em nossa Sociedade. Para isso, relatam-se resultados de uma reflexão sobre o papel do espaço, o espaço urbano, relações entre o Estado e o espaço, a difusão de inovações, relações entre transporte urbano e espaço, e a história resumida do transporte por trolebus no Brasil. Detalham-se a análise de dados sobre a operação de trolebus em cinco cidades, onde hoje (1994), se transporta passageiros com o ônibus elétrico no Brasil, resultados de análise da história do trolebus sob os conceitos resultantes da reflexão exposta e conclusões gerais que corroboram com a tese demonstrada. / This work reports a trial to demonstrate that the study of a set of information from discussions about the last decade Geography\'s way can allow the identification of concepts and useful processes to explain the relationships between urban transportation equipments and the State, the space and the innovation difusion process in our Society. For this some meditation results on the space\'s role, urban space, relationships between space and State or urban transportation and space, innovation diffusion, and the story of trolleybus in Brazil was related. The data analysis on operation of trolleys in five cities, where today (1994) passengers are conducted by eletric buses in Brazil and the results of the trolley story on the concepts results from the reflexion exposed and the general conclusion that cooperate with this thesis are detailed here.

Tese de mestrado. Transportes. Faculdade de Engenharia. Universidade do Porto. 2006

Thesis (Ph. D.)--New Jersey Institute of Technology, 2005. / Includes bibliographical references (p. 136-140). Also available online via the New Jersey Institute of Technology library website (http://www.library.njit.edu/etd/).

Since semiconductor process is constantly being improved, the complexity of system-on-chip is rising daily and we can place more and more elements on the same chip area. The system designers have been searching new methodology that can handle the complex systems and the environment which can quickly simulate the system-on-chip. It is brought forward that is raising the level of abstraction, as the design methodology of Electronic-System-Level (ESL). But system designers still need to decide the system architecture (the bus and PE connection status), and judge if the system could meet the performance and cost constraints by simulation results. For the very complex system, system designers will cost more and more time owning to the growth of design space to get the best system architecture. In this thesis, we propose a synthesis method to support automatic ESL design and help system designers to decide system architecture from large design space in short time. The method uses fast estimation method to estimate bus topology and memory allocation that affect the processing-elements¡¦ communication. By this method, we can find better system architecture which meets all constraints with the same amount of processing-elements.

The complexity of electronic system is increasing rapidly and many of the electronic systems   are   embedded   systems   implemented   as   system-on-chip   (SoC).   This increasing  complexity  of  SoC  leads  to  longer  test  application  time  (TAT).  One approach  to  reduce  the  TAT  is  to  perform  tests  to  several  cores  in  parallel,  which requests transporting test data in parallel instead of sequentially. In IEEE Std. 1500, it supports parallel test mode by incorporating a user-defined, parallel   test   access   mechanism   (TAM)   to   speed   up   the   testing   process.   The user-defined  TAM  means  the  detail  of  TAM  design  is  excluded  from  standard  and decided by system integrator. Therefore, we propose a customized TAM structure and two approaches to guarantee full-spatial-parallelism under a bus width limit, and aim to  minimize  the  total  number  of  wire  connections.  In  order  to  know  how  close  to optimal  solution  our  solutions  are,  we  implement  a  Simulated  Annealing  (SA) algorithm to do the comparison. The  experimental  results  of  the  two  proposed  approaches  based  on  benchmark ISCAS’89  and  ITC’02  show  the  parallelism  can  be  guaranteed  by  our  approaches while using only a few wire connections per pin, and the execution times of them are shorter compared with the SA algorithm.