In this Thesis, we propose a mechanism to dynamically adjust the video bit rates through the segmentation and the reassembly of SVC (Scalable Video Coding) segments in a P2P network. At the transmitter, an SVC film is segmented into a number of segments with different sizes. Each segment is further chopped into Torrents according to three scalabilities of SVC (Temporal, Quality, and Spatial). The Torrents with three scalabilities are referred to as 3D-Torrents. At the receiver, we present three approaches of grabbing Torrents (Temporal-First, Quality-First and Interleaving) form P2P networks to validate that the proposed 3D-Torrent reassembly can adapt to different bandwidths and to fit different hardware equipments so that any possible video freeze-up time can be avoided. To demonstrate how the proposed 3D-Torrent reassembly affect video bit rates in the P2P video streaming environment, we implement the segmentation, grabbing, and reassembly of Torrents on a Linux platform. In the P2P network built by Hadoop, we study (i) the video freeze-up time with/without adopting 3D-Torrent reassembly, (ii) video quality under different grabbing approaches using two different types of video, static and active background. To compare the video quality at the transmitter to that at the receiver, we modify the conventional PSNR equation. Two new dimensions, Temporal and Spatial, are included in the new PSNR3D equation to compare the video quality between the transmitter and the receiver. From the experimental results, we observe that the freeze-up time approaches zero using the 3D-Torrent reassembly and video bit rates can be dynamically adjusted according to the available bandwidth.

In the thesis, we investigate transmit beamforming strategies in a wireless cooperative network consisting of one source, one destination and multi relays that adopt amplify-and-forward (AF). In our scheme, small amount of information feedback from the destination, each relays perturbs individually based beamforming coefficient. Perturbation-based beamforming have been proposed in [16], where the authors assume that the channel is time-invariant, and every relay node can not acquire channel state information (CSI) after receiving pilot sequence signals, the relays multiply the pilot sequence with two perturbed beamforming vectors, and forward two weighted training sequence to destination. At the destination, the signal to noise ratio (SNR) of two received training sequence are evaluated and compared. Finally, the destination compare with SNRs. To indicate the result of compared SNRs, destination feedback one-bit message to inform relays the comparison results, and then relays update beamforming vector based on one-bit message. After several iteration, the beamforming vector will approach the optimum one. However, in time-varying environment, the updating rata of beamforming vector in the method with one-bit feedback may be more slowly than rate of channel variation. The contribution of this thesis is to propose transmit beamforming scheme with two-bit or finite-bit feedback to accommodate to the time-varying environment. In our proposed scheme, the destination linearly combines two received sequence corresponding to two different beamforming vectors with various weighting factors. After evaluating and comparing the SNRs of combined signals, the destination notifies the optimum linear combining factors using a multi-bit feedback message. Based on the feedback message, relays can update the beamforming vector correspondingly. In chapter five, it shows through computer simulations that our proposed scheme can raise average SNR and reduce bit error rate effectively.

In the Thesis, we propose a mechanism to dynamically adjust video parameters in an intelligent video surveillance network. Whenever there is an alarm or network encounters congestion, we could adjust video parameters including Frames per Second (FPS), Quality, and Picture Size to adapt to network bandwidth. For examples, we can adjust FPS when an alarm exists in the surveillance system; we can adjust the Quality or Picture Size by counting the total number of video packets received per second to obtain a smooth video when network is congested To demonstrate the proposed schemes, we implement these three adjustable parameters, Quality, Picture size, and FPS on a Linux platform. To do this, we establish a new HTTP connection from a client to a camera and then we develop the corresponding control messages issued by the client in order to change the video parameters. In addition, we implement a video recovery mechanism by measuring the differences in arrival time between every packet (referred to as diff). Finally, we observe with our proposed scheme whether the video quality can be smoother under different background traffics. In the video recovery mechanism, we utilize diff to decide whether a higher quality picture should be persisted or downgraded to a lower quality picture to avoid packet loss under network congestion.

Different wireless communication systems utilizing different standards and for multiple applications have penetrated the normal people's life, such as Cell phone, Wireless LAN, Bluetooth, Ultra wideband (UWB) and WiMAX systems. The wireless receiver normally serves as the primary part of the system, which heavily influences the system performance. This research concentrates on the designs of several important blocks of the receiver; multi-stage amplifier and low noise amplifier. Two novel multi-stage amplifier typologies are proposed to improve the bandwidth and reduce the silicon area for the application where a large capacitive load exists. They were designed using AMI 0.5 m µ CMOS technology. The simulation and measurement results show they have the best Figure-of-Merits (FOMs) in terms of small signal and large signal performances, with 4.6MHz and 9MHz bandwidth while consuming 0.38mW and 0.4mW power from a 2V power supply. Two Low Noise Amplifiers (LNAs) are proposed, with one designed for narrowband application and the other for UWB application. A noise reduction technique is proposed for the differential cascode Common Source LNA (CS-LNA), which reduces the LNA Noise Figure (NF), increases the LNA gain, and improves the LNA linearity. At the same time, a novel Common Gate LNA (CG-LNA) is proposed for UWB application, which has better linearity, lower power consumption, and reasonable noise performance. Finally a novel practical current injection built-in-test (BIT) technique is proposed for the RF Front-end circuits. If the off-chip component Lg and Rs values are well controlled, the proposed technique can estimate the voltage gain of the LNA with less than 1dB (8%) error.

In the thesis, we study the rearrangeability of the Banyan-type network with crosstalk constraint. Let $x$, $p$ and $c$ be nonnegative integers with $0leq x,cleq n$ and $n,pgeq 1$. $B_{n}(x,p,c)$ is the Banyan-type network with, $2^{n+1}$ inputs, $2^{n+1}$ outputs, $x$ extra-stages, and each connection containing at most $c$ crosstalk switch elements. We give the necessary and sufficient conditions for rearrangeable Banyan-type networks $B_{n}(x,p,c)$.

In this thesis, a highly efficient implementation of the channel decoder for terrestrial digital video broadcast (DVBT) standard is proposed. DVB-T channel decoder is mainly composed of four major modules including the inner Viterbi decoder, outer Reed-Solomon decoder and inner and outer de-interleaver modules which all require significant amount of intermediate data storage. The main contribution of this thesis is to propose suitable architectural solution for each individual module to achieve efficient realization of the data storage mostly by single-port memory blocks which can lead to the reduction of silicon area and the dynamic power dissipation. For the outer convolutional deinterleaver module, a special address generator has been proposed such that the data deinterleaver path can be merged and implemented as three memory blocks. For the inner symbol deinterleaver module, a lookahead technique has been applied to the design of address generator that can generate valid deinterleaving address each cycle to avoid the buffering problem. In addition, a novel deinterleaver memory partitioning architecture is proposed such that the entire deinterleaver can be built on four single-port memory banks. These four modules have been verified and integrated as a robust channel decoder silicon intellectual property (IP). Our implementation result shows that the core area of entire DVB-T channel decoder IP (Intellectual Property) can be realized in less than 6.8 mm2 in 0.18-µm TSMC technology.

No description available.

Equipment failure and well deviations are prevailing contributors to production delays within the petroleum industry. Particular monetary focus is given to the drilling operations of wells to overcome these deficits, in order to extract natural resources as efficiently, and as safely, as possible. The research presented here focuses on minimizing vibrations of the drill string near the bottom-hole assembly (BHA) by identifying the cause of external forcing on the drillstring in vertical and horizontal wells and measuring the effects of various factors on the stability of perturbations on the system. A test rig concept has been developed to accurately measure the interaction forces and torques between the bit, formation and fluids during drilling in order to clearly define a bit/formation interface law (BFIL) for the purpose vibrational analysis. As a secondary function, the rig will be able to measure the potential inputs to a drilling simulation code that can be used to model drillstring vibrations. All notable quantities will be measured including torque on bit (TOB), weight on bit (WOB), lateral impact loads (LIL), formation stiffness, bit specific properties, fluid damping coefficients and rate of penetration (ROP). The conceptual design has been analyzed and refined, in detail, to verify its operational integrity and range of measurement error. The operational envelope of the rig is such that a drill bit of up to 8 ½ inches in diameter can be effectively tested at desired operational parameters (WOB: 0-55,000 lbf, RPM: 60-200) with various rock formations and multiple fluid types. Future use and design possibilities are also discussed to enhance the functionality of the rig and the potential for further research in the area of oil and gas drilling and vibrational modeling.

Abstract Radio link adaptation, multiple antenna techniques, relaying methods and dynamic radio resource assignment are among the key methods used to improve the performance of wireless communication networks. Opportunistic resource block (RB) allocation in downlink orthogonal frequency division multiple access (OFDMA) with limited feedback is considered. The spectral efficiency analysis of multiuser OFDMA with imperfect feedback path, multiple antenna methods and relaying methods is a particular focus. The analysis is derived for best-M feedback methods and for a RB-wise signal-to-noise ratio (SNR) quantization based feedback strategy. Practical resource fair round robin (RR) allocation is assumed at the RB assignment, i.e., each user gets the same portion of the available RBs. The fading of each RB is modelled to be independent and identically distributed (IID). This assumption enabled a communication theoretic approach for the performance evaluation of OFDMA systems The event probabilities related to the considered OFDMA systems are presented so that the feedback bit error probability (BEP) is a parameter in the expressions. The performance expressions are derived for the BEP in the case of binary phase-shift keying (BPSK) modulation and single antenna methods. Asymptotic BEP behavior is considered for the best-M feedback methods when the mean SNR tends to infinity. The system outage capacity and the average system spectral efficiency are investigated in the case of multiple antenna schemes. Antenna selection and space-time block coding (STBC) are considered in multiple antenna schemes when each RB is allocated exclusively to a single user. Simple OFDMA-spatial division multiple access (SDMA) schemes are also analyzed when zero forcing (ZF) detection is assumed at the receiver. Relay enhanced dynamic OFDMA with single and multiple antennas at each end is considered for fixed infrastructure amplify-and-forward (AF) relaying methods. The average spectral efficiency has been derived for the best-M and RB-wise one bit feedback schemes, antenna selection and STBC methods. The best choice for a combination of multiple antenna scheme and feedback strategy depends on several system parameters. The proposed analytical tools enable easy evaluation of the performance of the investigated schemes with different system parameters. The fundamental properties of the combinations of feedback and multiple antenna schemes are extensively studied through numerical examples. The results also demonstrate that the analytical results with idealized IID fading assumption are close to those obtained via simulations in a practical frequency selective channel when RBs are selected properly. Dynamic RB allocation is attractive for practical OFDMA systems since significant performance gain over random allocation can be achieved with a practical allocation principle, very low feedback overhead and an imperfect feedback channel.

Cette thèse étudie l’électronique cryogénique et la réalisation de boîtes quantiques (QD) sur substrat SOI pour le calcul quantique. Deux technologies sont proposées pour la démonstration de boîtes quantiques d’électrons/trous. La première s’appuie sur les dispositifs Trigate SOI développés au CEA-LETI et la seconde exploite la technologie FD-SOI 28nm développée par STMicroelectronics. Dans un premier temps, les dispositifs à double-grille du LETI sont mesurés à très basse température (60mK) pour mettre en avant le principe d’exclusion de Pauli pour les premiers trous confinés à l’intérieur des deux QD. Au travers de cette expérience réalisée sur un double QD nous étudions une brique élémentaire permettant à terme l’initialisation et la lecture d’un qubit. Cette expérience a par la suite été étendue à d’autres dispositifs possédant quatre grilles pour lesquels un protocole de mesure est proposé pour la démonstration de deux qubits de spin d’électron. Dans un second temps, nous avons adressé la question du contrôle, de la lecture et de la manipulation des qubits de spin par une électronique pouvant fonctionner à basse température. Les performances digitales et analogiques des transistors FD-SOI ont été étudiées sur une large gamme de température. La réduction de la température montre une nette amélioration de la mobilité des électrons et des trous mais également une plus faible pente sous le seuil (SS) qui s’accompagne également d’une augmentation de la tension de seuil (Vth). La saturation de la SS pour les faibles températures est expliquée à l’aide d’un modèle analytique développé dans le cadre de cette thèse. En modélisant une queue étroite de densité d'états près des bords des bandes de conduction et de valence et en utilisant la statistique de Fermi-Dirac, un excellent accord est obtenu entre les mesures et le modèle. L’ajout d’une variation exponentielle dans la densité de pièges d’interface permet de reproduire l’évolution de la SS sur plus de 6 décades de courant. Par ailleurs, nous montrons que l’effet d’une polarisation face arrière qui permet d’ajuster la Vth des transistors FD-SOI pour viser des applications haute performance ou basse consommation fonctionne parfaitement à basse température. La modulation de la Vth reste la même de 300K à 4K pour les grandes et petites longueurs de grille des transistors NMOS/PMOS. Afin de tirer avantage de la technologie FD-SOI et d’évaluer son intérêt pour l’électronique cryogénique, nous avons caractérisé plusieurs oscillateurs en anneaux (RO) jusqu’à 4K. L’étude a été réalisée en deux temps. Dans un premier temps, l’augmentation de la Vth à basse température n’a pas été corrigée. Puis, cette augmentation de la Vth a été corrigée grâce à la polarisation face arrière afin de conserver la même Vth que celle mesurée à 300K. Afin de conserver les avantages tirés des plus fortes mobilités des porteurs à basse température, nous montrons que la Vth doit être corrigée pour réduire significativement le délai de commutation d’une chaine d’inverseurs. Nous montrons qu’à 4K un régime de fonctionnement optimal alliant à la fois haute performance et basse consommation peut être obtenu avec une tension d’alimentation (VDD) de 0.3V contre 1V à 300K. Cela permet de réduire de façon significative la dissipation statique et dynamique des RO. Un produit Energie-Délai de 6.9fJ.ps avec un délai par étage de 37ps sont obtenus à VDD = 0.325V grâce à l’utilisation de la polarisation face arrière. Pour finir, nous discutons de la dualité des transistors FD-SOI canal court qui peuvent être utilisés soit comme MOSFET ou comme transistors à électron unique. La présence de QD dans les transistors FDSOI est démontrée avec des caractéristiques proches de celles obtenues avec d’autres architectures (type nanofil) offrant ainsi des perspectives intéressantes pour une future co-intégration d’une électronique cryogénique avec des qubits de spin réalisés à partir d’une même plateforme industrielle. / This thesis studies cryogenic electronics and quantum dots on silicon-on-insulator (SOI) for quantum computing. Different types of electron and hole quantum dots are fabricated with Leti's SOI nanowire (NW) and planar 28nm FD-SOI technology. In the first part, Pauli Spin Blockade (PSB) is studied for the first holes down to 60mK. We show that it is governed by a strong spin orbit coupling (SOC). The intradot relaxation rate of 120kHz was found for the first holes. The access barriers tunability realized with additional gates was proven to be efficient regarding the isolation of qubit from source/drain metallic leads. Following the recent demonstration of electron-dipole spin resonance (EDSR) achieved in electron quantum dots confined in the corners of silicon nanowire (CDs), we deeply investigated quantum dots in several multi-gate samples under different body-biasing conditions. Based on preliminary cryogenic transport measurements, an operation protocol for a compact two electron spin qubit gate has been proposed.Regarding cryogenic electronics required for an efficient control, manipulation and read-out of a large number of qubits, the low temperature digital and analog performance of 28nm FD-SOI MOSFETs was analysed from room temperature down to 4K. Significant improvements in transistor performance are achieved with a clear enhancement of carrier mobility and a strong reduction of subthreshold swing (SS), even for short-channel devices with gate length down to 28nm. The saturation of the subthreshold swing at low temperature is explained with a new analytical model developed in this thesis. By introducing a narrow tail in the density of states at the edges of the conduction and valence bands and using the Fermi-Dirac statistics, an excellent agreement of SS is achieved between experiments and modelling. The analysis of the SS-IDS metric under different forward body-biasing (FBB) conditions has revealed that the increased density of interface traps cannot be responsible for the SS saturation at low temperature. By adding a slight exponential variation in the interface trap density, we show that the SS-IDS curve can be well reproduced over more than 6 decades, paving a way for an efficient cryogenic design of CryoCMOS.In a second time, cryogenic performance of Ring Oscillators (RO) down to 4K was investigated. We have shown that the optimal supply voltage can be reduced down to 0.3V. This allows to efficiently reduce the dynamic and static power dissipations. At the same time, a small Energy-Delay product of 6.9fJ.ps with a delay per stage of 37ps were achieved at VDD=0.325V under aggressive FBB.Finally, in the last chapter, the duality of short-channel FD-SOI transistors operation as FETs or SETs is demonstrated at 4K. By benchmarking the QDs with respect to the common silicon platforms, we show that 28nm FD-SOI technology has a great potential for both cryogenic electronics and qubits.