L’évolution tendant à réduire la taille et augmenter la complexité des circuits électroniques modernes, est en train de ralentir du fait des limitations technologiques, qui génèrent beaucoup de d’imperfections et de defaults durant la fabrication ou la durée de vie de la puce. Les FPGAs sont utilisés dans les systèmes numériques complexes, essentiellement parce qu’ils sont reconfigurables et rapide à commercialiser. Pour garder une grande fiabilité de tels systèmes, les FPGAs doivent être testés minutieusement pour les defaults. L’optimisation de l’architecture des FPGAs pour l’économie de surface et une meilleure routabilité est un processus continue qui impacte directement la testabilité globale et de ce fait, la fiabilité. Cette thèse présente une stratégie complète pour le test et le diagnostique des defaults de fabrication des “mesh-based FPGA” contenant une nouvelle topologie d’interconnections à plusieurs niveaux, ce qui promet d’apporter une meilleure routabilité. Efficacité des schémas proposes est analysée en termes de temps de test, couverture de faute et résolution de diagnostique. / The evolution trend of shrinking feature size and increasing complexity in modern electronics is being slowed down due to physical limits that generate numerous imperfections and defects during fabrication steps or projected life time of the chip. Field Programmable Gate Arrays (FPGAs) are used in complex digital systems mainly due to their reconfigurability and shorter time-to-market. To maintain a high reliability of such systems, FPGAs should be tested thoroughly for defects. FPGA architecture optimization for area saving and better signal routability is an ongoing process which directly impacts the overall FPGA testability, hence the reliability. This thesis presents a complete strategy for test and diagnosis of manufacturing defects in mesh-based FPGAs containing a novel multilevel interconnects topology which promises to provide better area and routability. Efficiency of the proposed test schemes is analyzed in terms of test cost, respective fault coverage and diagnostic resolution.

With the rapid development of wireless and wireline communications, a variety of new standards and applications are emerging in the marketplace. In order to achieve higher levels of integration, RF circuits are frequently embedded into System on Chip (SoC) or System in Package (SiP) products. These developments, however, lead to new challenges in manufacturing test time and cost. Use of traditional RF test techniques requires expensive high frequency test instruments and long test time, which makes test one of the bottlenecks for reducing IC costs. This research is in the area of built-in self test technique for RF subsystems. In the test approach followed in this research, on-chip detectors are used to calculate circuits specifications, and data converters are used to collect the data for analysis by an on-chip processor. A novel on-chip amplitude detector has been designed and optimized for RF circuit specification test. By using on-chip detectors, both the system performance and specifications of the individual components can be accurately measured. On-chip measurement results need to be collected by Analog to Digital Converters (ADCs). A novel time domain, low power ADC has been designed for this purpose. The ADC architecture is based on a linear voltage controlled delay line. Using this structure results in a linear transfer function for the input dependent delay. The time delay difference is then compared to a reference to generate a digital code. Two prototype test chips were fabricated in commercial CMOS processes. One is for the RF transceiver front end with on-chip detectors; the other is for the test ADC. The 940MHz RF transceiver front-end was implemented with on-chip detectors in a 0.18 [micrometer] CMOS technology. The chips were mounted onto RF Printed Circuit Boards (PCBs), with tunable power supply and biasing knobs. The detector was characterized with measurements which show that the detector keeps linear performance over a wide input amplitude range of 500mV. Preliminary simulation and measurements show accurate transceiver performance prediction under process variations. A 300MS/s 6 bit ADC was designed using the novel time domain architecture in a 0.13 [micrometer] standard digital CMOS process. The simulation results show 36.6dB Signal to Noise Ratio (SNR), 34.1dB Signal to Noise and Distortion Ratio (SNDR) for 99MHz input, Differential Non-Linearity (DNL)<0.2 Least Significant Bit (LSB), and Integral Non-Linearity (INL)<0.5LSB. Overall chip power is 2.7mW with a 1.2V power supply. The built-in detector RF test was extended to a full transceiver RF front end test with a loop-back setup, so that measurements can be made to verify the benefits of the technique. The application of the approach to testing gain, linearity and noise figure was investigated. New detector types are also evaluated. In addition, the low-power delay-line based ADC was characterized and improved to facilitate gathering of data from the detector. Several improved ADC structures at the system level are also analyzed. The built-in detector based RF test technique enables the cost-efficient test for SoCs. / text

Cette thèse vise l’étude de techniques de type BIST pour un front-end RF, considérant des nouveaux types des capteurs intégrés très simples pour l’extraction de signaux. Ces signaux et les stimuli de test associés seront par la suite traités par des algorithmes de l’apprentissage automatique qui devront permettre une prédiction des performances des différents blocs du système. Une évaluation des capteur proposés en tant que métriques de test paramétrique et couverture des fautes catastrophique sera nécessaire pour pouvoir aboutir à des techniques de test à bas coût pour le test de production, permettant une réduction importante du coût de revient des produits. / This thesis aims to study techniques such BIST for RF front-end, whereas new types of simple integrated sensors for signal extraction. These signals and stimuli associated test will then be processed by machine learning algorithms that will allow prediction of the performance of different blocks of the system. An evaluation of the proposed sensor as parametric test metrics and coverage of catastrophic faults will be needed to reach test techniques for low-cost production test, allowing a significant reduction in the cost of products

Two-dimensional scan design is an effective BIST architecture that uses multiple scan chains in parallel to test the Circuit Under Test (CUT). Linear Finite State Machines (LFSMs) are often used as on-board Pseudo Random Pattern Generators (PRPGs) in two-dimensional scan designs. However, linear dependencies present in the LFSM generated test-bit sequences adversely affect the resultant fault coverage in two-dimensional scan designs. In this work, we present methods that improve the resultant fault coverage in two-dimensional scan designs through the minimization of linear dependencies. Currently, metric of channel separation and matrix-based metric are used in order to estimate linear dependencies in a CUT. When the underlying sub-circuit (cone) structure of a CUT is available, the matrix-based metric can be used more effectively. Fisrt, we present two methods that use matrix-based metric and minimize the overall linear dependencies in a CUT through explicitly minimizing linear dependencies in the highest number of underlying cones of the CUT. The first method minimizes linear dependencies in a CUT through the selection of an appropriate LFSM structure. On the other hand, the second method synthesizes a phase shifter for a specified LFSM structure such that the overall linear dependencies in a CUT are minimized. However, the underlying structure of a CUT is not always available and in such cases the metric of channel separation can be used more effectively. The metric of channel separation is an empirical measure of linear dependencies and an ad-hoc large channel separation is imposed between the successive scan chains of a two-dimensional scan design in order to minimize the linear dependencies. Present techniques use LFSMs with additional phase shifters (LFSM/PS) as PRPGs in order to obtain desired levels of channel separation. We demonstrate that Generalized LFSRs (GLFSRs) are a better choice as PRPGs compared to LFSM/PS and obtain desired levels of channel separations at a lower hardware cost than the LFSM/PS. Experimental results corroborate the effectiveness of the proposed methods through increased levels of the resultant fault coverage in two-dimensional scan designs.

No description available.

With the increase of device complexity and test-data volume required to guarantee adequate defect coverage, external testing is becoming increasingly difficult and expensive. Logic Built-in Self Test (LBIST) is a viable alternative test strategy as it helps reduce dependence on an elaborate external test equipment, enables the application of a large number of random tests, and allows for at-speed testing. The main problem with LBIST is suboptimal fault coverage achievable with random vectors. LFSR reseeding is used to increase the coverage. However, to achieve satisfactory coverage, one often needs a large number of seeds. Computing a small number of seeds for LBIST reseeding still remains a tremendous challenge, since the vectors needed to detect all faults may be spread across the huge LFSR vector space. In this work, we propose new methods to enable the computation of a small number of LFSR seeds to cover all stuck-at faults as a first-order satisfiability problem involving extended theories. We present a technique based on SMT (Satisfiability Modulo Theories) with the theory of bit-vectors to combine the tasks of test-generation and seed computation. We describe a seed reduction flow which is based on the `chaining' of faults instead of pre-computed vectors. We experimentally demonstrate that our method can produce very small sets of seeds for complete stuck-at fault coverage. Additionally, we present methods for inserting test-points to enhance the testability of a circuit in such a way as to allow even further reduction in the number of seeds. / Master of Science

While conventional test point insertions commonly used in design for testability can improve fault coverage, the test points selected may not necessarily be the best candidates to aid <em>silicon diagnosis</em>. In this thesis, test point insertions are conducted with the aim to detect more faults and also synergistically distinguish currently indistinguishable fault-pairs. We achieve this by identifying those points in the circuit, which are not only hard-to-test but also lie on distinguishable frontiers, as Testability-Diagnosability (TD) points. To this end, we propose a novel low-cost metric to identify such TD points. Further, we propose a new DFT + DFD architecture, which adds just one pin (to identify test/functional mode) and small additional combinational logic to the circuit under test. Our experiments indicate that the proposed architecture can distinguish 4x more previously indistinguishable fault-pairs than existing DFT architectures while maintaining similar fault coverages. Further, the experiments illustrate that quality results can be achieved with an area overhead of around 5%. Additional experiments conducted on hard-to-test circuits show an increase in <em>fault coverage</em> by 48% while maintaining similar diagnostic resolution. Built-in Self Test (BIST) is a technique of adding additional blocks of hardware to the circuits to allow them to perform self-testing. This enables the circuits to test themselves thereby reducing the dependency on the expensive external automated test equipment (ATE). At the end of a test session, BIST generates a signature which is a compaction of the obtained output responses of the circuit for that session. Comparison of this signature with the reference signature categorizes the circuit as error free or buggy. While BIST provides a quick and low cost alternative to check circuit's correctness, diagnosis in BIST environment remains poor because of the limited information present in the lossily compacted final signature. The signature does not give any information about the possible defect location in the circuit. To facilitate diagnosis, researchers have proposed the use of two additional on-chip embedded memories,response memory to store reference responses and fail memory to store failing responses. We propose a novel architecture in which only one additional memory is required. Experimental results conducted on benchmark circuits substantiate that the same fault coverage can be maintained using just 5% of the available test vectors. This reduces the size of memory required to store responses which in turn reduces area overhead. Further, by adding test points to the circuit using our proposed architecture, we can improve the diagnostic resolution by 60% with respect to external testing. / Master of Science

The objective of this dissertation is to propose circuit architectures and techniques for built-in test and calibration of phase-locked loops. The design of phase-locked loops is first investigated to achieve a robust performance over process, temperature, voltage corners with minimum overhead. Different design techniques including adding loop programmability, increasing area efficiency, reducing noise immunity, and increasing frequency coverage are discussed. Secondly, built-in testing of phase-lock loops using sensors are proposed for loop dynamic parameters and reference spur. An integrator is designed to extract the subtle response from the system so that target parameters can be predicted. Different testing methodologies are applied different specification testing as well. Finally, an on chip phase-locked loop design is implemented for reference spur calibration. The phase-locked loop is designed with a programmable reference spur range. A static phase offset detector is included to identify the optimal setting of reference spur in the feedback system. The integrated jitter performance is improved by the calibration mechanism. The results of this thesis serve as an on-chip built-in self-test and self-calibration solution for embedded phase-locked loops in a high integration system.

abstract: This dissertation proposes and presents two different passive sigma-delta modulator zoom Analog to Digital Converter (ADC) architectures. The first ADC is fullydifferential, synthesizable zoom-ADC architecture with a passive loop filter for lowfrequency Built in Self-Test (BIST) applications. The detailed ADC architecture and a step by step process designing the zoom-ADC along with a synthesis tool that can target various design specifications are presented. The design flow does not rely on extensive knowledge of an experienced ADC designer. Two example set of BIST ADCs have been synthesized with different performance requirements in 65nm CMOS process. The first ADC achieves 90.4dB Signal to Noise Ratio (SNR) in 512µs measurement time and consumes 17µW power. Another example achieves 78.2dB SNR in 31.25µs measurement time and consumes 63µW power. The second ADC architecture is a multi-mode, dynamically zooming passive sigma-delta modulator. The architecture is based on a 5b interpolating flash ADC as the zooming unit, and a passive discrete time sigma delta modulator as the fine conversion unit. The proposed ADC provides an Oversampling Ratio (OSR)- independent, dynamic zooming technique, employing an interpolating zooming front-end. The modulator covers between 0.1 MHz and 10 MHz signal bandwidth which makes it suitable for cellular applications including 4G radio systems. By reconfiguring the OSR, bias current, and component parameters, optimal power consumption can be achieved for every mode. The ADC is implemented in 0.13 µm CMOS technology and it achieves an SNDR of 82.2/77.1/74.2/68 dB for 0.1/1.92/5/10MHz bandwidth with 1.3/5.7/9.6/11.9mW power consumption from a 1.2 V supply. / Dissertation/Thesis / Doctoral Dissertation Electrical Engineering 2018

Le test de production des imageurs CMOS est une étape clé du flot de fabrication afin de garantir des produits répondant aux critères de qualité et exempts de défauts de fabrication. Ces tests sont classifiés en test électrique et test optique. Le test électrique est basé sur du test structurel qui vérifie la partie numérique et certain blocks analogiques. La plus grande partie des circuits analogiques et la matrice des capteurs sont testés par le test optique. Ce test est basé sur des captures d'images et sur une recherche des défauts au moyen d'algorithmes de calcul spécifiques appliqué sur les images. Proche du fonctionnement applicatif, ils sont qualifies de test fonctionnels. La couverture des défauts obtenue par les tests de type fonctionnel est généralement inférieure à celle obtenue par un test structurel. L'objectif de cette thèse est d'étudier et développer des solutions de test alternatives aux tests fonctionnels afin d'obtenir des meilleurs taux de couverture de défauts, améliorant ainsi la fiabilité, tout en réduisant le temps de test et son coût. Parmi les défauts optiques qui ont causé des retours client par le passés, le défaut qui présent Horizontal Fixed Pattern Noise (HFPN) donnent lieu à un taux de couverture insuffisant. Ces recherches ont été orientées vers l'amélioration du taux de couverture de défauts dite de HFPN dans le test de production des imageurs CMOS.Le HFPN est défini comme une sorte d'image défaillante qui présente sous la forme des bandes résiduelles horizontales. Il est principalement causé par les défauts dans les lignes d'interconnexion qui alimentent et pilotent les pixels. La détection d'un défaut HFPN dans les tests optiques actuels est par comparer les valeurs moyennes de chaque ligne de pixels avec les lignes adjacentes. Si la différence d'une ligne par rapport aux lignes adjacentes est supérieur à la limites spécifié, la ligne est constaté comme défectueuse. Cette limite est donc difficile d'être ajusté face à un compromis entre le taux de couverture de ce défaut et le rendement.Dans cette thèse, nous avons proposé d'abord une amélioration de l'algorithme de détection pour améliorer le test optique actuelle. L'amélioration de test optique est validée par des résultats de test en production en appliquant le nouvel algorithme. Par la suite, une technique d'auto test (BIST) pour la détection des défauts dans les lignes d'interconnexion de matrice des pixels est étudiée et évalué. Enfin, une puce imageur avec le technique d'auto test embarqué est conçu et fabriqué pour la validation expérimentale. / Current production testing of CMOS imager sensors is mainly based on capturing images and detecting failures by image processing with special algorithms. The fault coverage of this costly optical test is not sufficient given the quality requirements. Studies on devices produced at large volume have shown that Horizontal Fixed Pattern Noise (HFPN) is one of the common image failures encountered on products that present fault coverage problems, and this is the main cause of customer returns for many products. A detailed analysis of failed devices has demonstrated that HFPN failures arise from changes of electronic circuit topology in pixel addressing decoders or the metal lines required for pixel powering and control. These changes are usually due to the presence of spot defects, causing some pixels in a row to operate incorrectly, leading to an HFPN failure. Moreover, defects resulting in partially degraded metal lines may not induce image failure in limited industrial test conditions, passing the optical tests. Later, these defects may produce an image failure in the field, either because the capture conditions would be more stringent, or because the defects would evolve into catastrophic faults due to electromigration. In this paper, we have first enhanced the HFPN detection algorithm in order to improve the fault coverage of the optical test. Next, a built-in self-test structure is presented for the on-chip detection of catastrophic and non-catastrophic defects in the pixel power and control lines.