During recent years the thickness of the gate oxide has been reduced considerably. The progressive miniaturization of devices has caused several phenomena to emerge such as quasi-breakdown, direct tunneling and stress induced leakage currents. Such phenomena significantly modify the performance of the scaled-down MOSFETs. As a part of this research work, an effort has been made to study the performance and characteristics of the thin Gate oxide for MOSFETs and Tunnel Oxide for Floating Gate (FG) MOS devices. The exponential dependence of tunnel current on the oxide-electric field causes some critical problems in process control. A very good process control is therefore required. This can be achieved by finding out the exact value of F-N tunneling parameter. This research work also is an effort of finding an accurate value for parameter B and its dependence on the oxide thickness as the device are scaled down to a level where the probability of Direct Tunneling mechanism gains more prominence. A fully automated Low Current Measurement workstation with noise tolerance as low as 10-15 A was set up as a part of this research. C-V and I-V curves were analyzed to extract, determine and investigate the oxide thickness dependence of F-N parameter B. For oxide thickness in the range10~13 nm, the parameter B ranged between 260 and 267. Thus it can be said that it is not sensitive to the change in oxide thickness in this range. However it was noticed that for thickness around 7nm wide variety of results were obtained for the Fowler-Nordheim parameter B (B ranged from 260 to 454). This can be attributed to the enhancement in the leakage current due to the direct tunneling. Hence to have tight control over VT for a NVM, new algorithms need to be developed for even better process control for oxide thickness in the range of 7 nm and below.

Kyoto University (京都大学) / 0048 / 新制・課程博士 / 博士(工学) / 甲第15668号 / 工博第3326号 / 新制||工||1502(附属図書館) / 28205 / 京都大学大学院工学研究科電気工学専攻 / (主査)教授 引原 隆士, 教授 木本 恒暢, 教授 和田 修己 / 学位規則第4条第1項該当

In this dissertation, we investigates the electrical stress induced degradation in low-temperature polycrystalline-silicon thin film transistors (LTPS TFTs) applied for system-on-panel (SOP), including the electrical degradations of device for switch operation in active matrix flat-panel displays, driving circuit and nonvolatile memory. Finally, we also present the reliability of LTPS TFTs applied for flexible displays. In first part, electrical degradation of conventional and pattered metal-shielding LTPS TFTs under darkened and illuminated dynamic AC stresses are investigated. Experimental results reveal that competitive mechanisms are generated in conventional LTPS TFTs during illuminated stress, namely, carrier increase and electric field weakening. This phenomenon is verified by stressing the patterned source/drain open metal-shielding LTPS TFTs, which determines that the electric field weakening dominates; conversely, the carrier increase is dominated the electrical degradation in channel open metal-shielding device under illuminated stress. In addition, an improvement in anomalous on-current and subthreshold swing (S.S.) in n-channel LTPS TFTs after positive gate bias stress are studied. These improved electric properties are due to the hole trapping at SiO2 above the lightly doped drain regions, which causes a strong electric field at the gate corners. The effect of the hole trapping is to reduce the effective channel length and the S.S.. Besides, the stress-related electric field was also simulated by TCAD software to verify the mechanism above. Secondly, a mechanism of anomalous capacitance in p-channel LTPS TFTs was investigated. In general, the effective capacitance of the LTPS TFTs was only dependent with the overlap area between gate and source/drain under the off-state. However, the experimental results reveal that the off-state capacitance was increased with decreasing measurement frequency and/or with increasing measurement temperature. Besides, by fitting the curve of drain current versus electric field under off-state region, it was verified that the TAGIDL is consisted of the Pool-Frenkel emission and Thermal-Field emission. In addition, the charge density calculated from the Cch-Vg measurement also the same dependence with electric field. This result demonstrates that the anomalous capacitance is mainly due to the trap-assisted-gate-induced-drain-leakage (TAGIDL). In order to suppress the anomalous capacitance, a band-to-band hot electron (BTBHE) stress was utilized to reduce the vertical electric field between the gate and the drain. In third part, in order to realize the reliability in p-channel TFTs under illuminated environment operation, the degradation of negative bias temperature instability (NBTI) with illumination effect is investigated. The generations of interface state density (Nit) are identical under various illuminated intensity DC NBTI stresses. Nevertheless, the degradation of the grain boundary trap (Ntrap) under illumination was more significant than for the darkened environment, with degradation increasing as illumination intensity increases. This phenomenon is mainly caused by the extra number of holes generated during the illuminated NBTI stress. The increased Ntrap degradation leads to an increase in the darkened environment leakage current. This indicates that more traps are generated in the drain junction region that from carrier tunneling via the trap, resulting in leakage current. Conversely, an increase of Ntrap degradation results in a decrease in the photoleakage current. This indicates that the number of recombination centers increases in poly-Si bulk, affecting photosensitivity in LTPS TFTs. Besides, the transient effect assisted NBTI degradation in p-channel LTPS TFTs under dynamic stress is also presented, in which the degradation of the Ntrap becomes more significant as rise time decreases to 1 £gs. Because the surface inversion layer cannot form during the short rise time, transient bulk voltage will cause excess holes to diffuse into the poly-Si bulk. Therefore, the significant Ntrap increase is assisted by this transient effect. Fourthly, we study the electric properties of n- and p-channel LTPS TFTs under the mechanical tensile strain. The improved on-current for tensile strained n-channel TFTs is originated form an increase in energy difference between 2- and 4-fold valleys, reducing the inter-valley scattering and further improving the carrier mobility. On the contrary, the hole mobility decreases in p-channel, suggesting the split between the light hole and heavy hole energy bands and an increase in hole population on the heavy hole energy band of poly-Si when the uniaxial tensile strain is parallel to the channel direction. In addition, the Nit and Ntrap degradations induced by NBTI for tensile strained LTPS TFTs are more pronounced than in the unstrained. Extracted density-of-states (DOS) and conduction activation energy (EA) both show increases due to the strained Si-Si bonds, which implies that strained Si-Si bonds are able to react with dissociated H during the NBTI stress. Therefore, the NBTI degradation is more significant after tensile strain than in an unstrained condition. Finally, the SONOS-TFT applied to nonvolatile memory is prepared and studied. In the gate disturb stress, a parasitic capacitance and resistance in off-state region are identified as electrons trapped in the gate-insulator (GI) near the defined gate region. Meanwhile, these trapping electrons induced depletions in source/drain also degraded the I-V characteristic when the gate bias is larger than the threshold voltage. However, these degradations slightly recover when the trapped electrons are removed after negative bias stress. The electric field in the undefined gate region is also verified by TCAD simulation software.

Le travail de thèse effectué porte sur la caractérisation électrique et la modélisation du gaz d’électrons à deux dimensions (2D) dans les dispositifs MOS-HEMT à base de l’hétérojonction AlGaN/AlN/GaN. Ces dispositifs ont un fort potentiel pour les applications d'électronique de puissance. Ce travail de recherche se place en soutien aux efforts de recherche pour l’élaboration des épitaxies GaN sur Si et pour les filières technologiques HEMT sur GaN. Il s'agit de comprendre précisément le fonctionnement du gaz d'électrons 2D et ses propriétés de transport électronique. Une nouvelle méthodologie a été développée pour identifier le dopage résiduel de la couche GaN, lequel est un paramètre important des substrats GaN et était par ailleurs difficile à évaluer. Un deuxième axe de recherche a consisté à proposer des techniques de mesure fiables ainsi qu’une modélisation des propriétés de transport du gaz d'électrons 2D. Dans ce cadre, des mesures split-CV et effet Hall ont été réalisées en fournissant pour chacune d’elles un protocole expérimental adéquat, avec un montage innovant pour les mesures effet Hall. Ce travail expérimental a été enrichi par une modélisation des propriétés du transport du 2DEG basée sur le formalisme de Kubo-Greenwood. Enfin, dans un dernier axe de recherche, un aspect plus général visant la compréhension en profondeur de l’électrostatique de l’empilement de la grille de nos GaN-MOS-HEMT a été proposé. Il est basé sur la caractérisation électrique C-V, la modélisation et l’extraction des paramètres. Le modèle développé a permis de souligner l'impact des charges surfaciques de polarisation et des défauts sur la tension de seuil des MOS-HEMT. Ce modèle a également permis d’estimer une valeur de la déformation dans les couches GaN épitaxiées sur un substrat Silicium. / This thesis aims at studying the electrical characterization and modelling of two-dimensional (2D) electron gas in MOS-HEMT devices based on the hetero-junction AlGaN/AlN/GaN. These devices are very promising candidates for power electronics applications. This research work provides the production team with detailed data on phenomena affecting GaN material. The goal is to understand precisely how 2D electron gas works and evaluate its electronic transport properties. A new methodology has been developed to identify residual doping of the GaN layer. This method was developed in order to answer a real need to know this doping to determine the quality of the epitaxial GaN layer. The second research priority was to provide reliable measurement techniques and modelling of the transport properties of 2D electron gas. Within this framework, the split-CV and Hall effect measurements were carried out by providing for each of them a suitable experimental protocol, with an innovative set-up for Hall effect measurements. In addition, this experimental work was supported by modelling the transport properties of 2DEG based on Kubo-Greenwood's formalism. Finally, a more general aspect aimed at an in-depth understanding of the electrostatic stacking of the GaN-MOS-HEMT gate. It is based on C-V electrical characterization, modelling and parameter extraction. The model developed made it possible to highlight the impact of polarization surface charges and defects on the threshold voltage of MOS-HEMT. This model also contributed to the estimation of the value of deformation in epitaxial GaN layers on a Silicon substrate.