In the context of emerging non-volatile memory (NVM) where data structures can persist in-memory and are accessed through CPU loads and stores, we study how to efficiently manage data evolution. This is an extensively applied problem in both the scientific and business domains and is rapidly becoming an important component for a wider range of applications. We argue that the best way to achieve a smoother transition to the new programming model is to design a solution that is non-intrusive and generic i.e. not bound to a specific data model. We propose a novel library-level approach where the user can manage historical data directly from programming language code. This is achieved with a combination of two software layers: REWIND and VARIANT. At the bottom, lies REWIND (REcovery Write-Ahead System for In- Memory Non-Volatile Data Structures) which handles the low level specifics of NVM by dealing with write-ordering problems that arise in such context and allows recoverability of arbitrary data structures. Then, VARIANT (Versioning ARbItrary dAta structures in Non-volatile memory for Time-travel) focuses on versioning and time travel (moving between versions). We adopt a logging approach and we tightly integrate both systems for best performance by utilizing a common physical log of memory operations. With REWIND, we propose a novel recoverable log structure that permits atomic and durable appends and removals of log records. This is the keystone for building recoverable systems on top of NVM. Because latencies in recent NVM technologies such as Phase-change memory (PCM) are asymmetric, we propose novel techniques for reducing the write pressure of the recoverable log as well as mitigating the effect of synchronization control primitives such as memory fences (enhanced for NVM), i.e. barriers that enforce ordering and persistence to preceding instructions. We also propose different implementations for trading logging performance for rollback performance when this is appropriate. Finally, we revisit state-of-the-art recovery algorithms for the new context given the different latencies and synchronization control. Our results clearly indicate that current approaches for recoverability are ill-fitted for persisting data structures in the new context and it is possible to achieve low-overhead logging with customized mechanisms. Next, we focus on data evolution. We expose a simple API that allows versioning and time travel with minimal intrusiveness. We propose mechanisms for efficient and transparent cloning of Versionable data structures. This allows high concurrency since past images are returned as copies of the original data structure which remains intact. Then, we propose novel indexing techniques that significantly improve time travel performance as well as cloning with lazy schemes. We achieve a low overhead architecture by employing a mix of volatile and non-volatile data structures as well as hybrid structures that reside in both volatile and non-volatile memories. We perform an extensive evaluation of the proposed techniques and conclude that, in our context, by carefully mitigating the drawbacks of physical logging it is possible to create efficient systems for managing data evolution that are both data structure agnostic and non-intrusive.

Τις τελευταίες δεκαετίες, η ανάπτυξη των non-volatile μνημών (NVMs) κατέστησε ικανή την αντικατάσταση volatile μνημών, όπως των DRAMs και των μαγνητικών σκληρών δίσκων (HDDs), σε caching και storage εφαρμογές, αντίστοιχα. Οι δίσκοι στερεάς κατάστασης (SSDs) που βασίζονται σε NAND Flash μνήμες έχουν ήδη αναδειχθεί ως ένα χαμηλού κόστους, υψηλής απόδοσης και αξιόπιστο μέσο στα σύγχρονα συστήματα αποθήκευσης. Επιπλέον, οι ιδιότητες των υλικών αλλαγής φάσης και η πρόσφατη κλιμάκωση της Phase-Change μνήμης (PCM), την καθιστά ένα τέλειο υποψήφιο για την ανάπτυξη μνημών τυχαίας προσπέλασης αλλαγής φάσης (PCRAMs). Η ραγδαία κλιμάκωση των NVMs, με διαδικασίες ολοκλήρωσης κάτω από 19nm, και η χρήση της multi-level cell (MLC) τεχνολογίας συνέβαλλαν στην αύξηση της πυκνότητας αποθήκευσης πληροφορίας και συνεπώς μείωσαν το κόστος αποθήκευσης δραματικά. Ωστόσο, η διάρκεια ζωής των NV μνημών δεν παρέμεινε ανεπηρέαστη. Διαφορετικές παρεμβολές και πηγές θορύβου σε συνδυασμό με την επίδραση της γήρανσης έχουν ένα μεγάλο αντίκτυπο στην αξιοπιστία και την αντοχή αυτών των τεχνολογιών μνήμης, και ως εκ τούτου, των συστημάτων αποθήκευσης στα οποία χρησιμοποιούνται (SSDs, PCRAMs). Πολλές μέθοδοι και τεχνικές, όπως η μέθοδος wear-leveling, εξειδικευμένοι κώδικες ανίχνευσης και διόρθωσης λαθών (ECC) και τεχνικές pre-coding έχουν χρησιμοποιηθεί για να αντισταθμίσουν αυτές τις επιπτώσεις, ενώ άλλες, πιο περίπλοκες μεν, αλλά και πιο αποτελεσματικές, όπως η δυναμική προσαρμογή των κατωφλίων ανάγνωσης, βρίσκονται σε πειραματικό στάδιο. Η ανάπτυξη αυτών των τεχνικών βασίζεται στον πειραματικό χαρακτηρισμό των NV μνημών, τόσο σε επίπεδο κελιού όσο και σε επίπεδο ολοκληρωμένου κυκλώματος. Ο χαρακτηρισμός αυτός σχετίζεται με την μέτρηση του λόγου του αριθμού των bit σφαλμάτων προς τον αριθμό των συνολικών bits (BER) και το χρόνο απόκρισης (ανάγνωσης και εγγραφής) καθ' όλη τη διάρκεια ζωής της μνήμης, για διάφορες μορφές δεδομένων και σενάρια χρονισμών. Η διαδικασία αυτή, μέχρι τώρα, γίνεται με τη χρήση της πραγματικής NV μνήμης, συνήθως με ολοκληρωμένα κυκλώματα που βρίσκονται στο στάδιο της προ-παραγωγής, ενώ πιο ενδελεχής έλεγχος γίνεται στο τελικό στάδιο της παραγωγής. Αυτή η προσέγγιση έχει δύο σημαντικά μειονεκτήματα. Από τη μία πλευρά, είναι μια πολύ χρονοβόρα διαδικασία, δεδομένου ότι η γήρανση μίας NVM μπορεί να απαιτεί ένα μεγάλο αριθμό από program / erase (P/E) κύκλους που πρέπει να εκτελεστούν για κάθε πείραμα. Ο αριθμός αυτός κυμαίνεται από κάποιες δεκάδες χιλιάδες (NAND Flash) έως και κάποια εκατομμύρια κύκλους (PCM). Από την άλλη πλευρά, τα χαρακτηριστικά γήρανσης μίας NVM είναι αναλόγως εξαρτώμενα από τον αριθμό των Ρ/Ε κύκλων που εκτελούνται, καθιστώντας έτσι αδύνατη την διεξαγωγή διαφορετικών ή διαδοχικών πειραμάτων στην ίδια κατάσταση γήρανσης της μνήμης. Σε αυτή την εργασία παρουσιάζουμε ένα μοντέλο που αντιπροσωπεύει με ακρίβεια τη διαδικασία γήρανσης NV μνημών, αντιμετωπίζοντας τες ως ένα χρονικά μεταβαλλόμενο κανάλι επικοινωνίας βασισμένο σε ένα μη συμμετρικό n-PAM μοντέλο. Με βάση τη μοντελοποίηση των χαρακτηριστικών γήρανσης, υλοποιούμε ένα σύστημα εξομοίωσης σε πραγματικό χρόνο και με μεγάλη ακρίβεια της συμπεριφοράς NV-μνημών, κάτω από ορισμένες από το χρήστη συνθήκες γήρανσης, σε τεχνολογία FPGA. Η πλατφόρμα που παρουσιάζεται στην παρούσα εργασία βασίζεται σε μια αναπροσαρμόσιμη αρχιτεκτονική υλικού και λογισμικού που επιτρέπει την ακριβή εξομοίωση των νέων και αναδυόμενων τεχνολογιών και μοντέλων των NVMs. Η πλατφόρμα που αναπτύχθηκε μπορεί να αποτελέσει ένα πολύτιμο εργαλείο για την ανάπτυξη και αξιολόγηση αλγορίθμων και τεχνικών κωδικοποίησης. / Over the last few years, non-volatle memory (NVM) has shown a great potential in replacing volatile memory, like DRAM in caching applications, and magnetic HDDs in storage applications. NAND Flash-based solid state drives (SSDs) have already emerged as a low-cost, high-performance and reliable storage medium for both commercial and enterprise storage systems. Additionally, the properties of phase-change materials and the recent scaling of Phase-Change Memory (PCM) has made it a perfect candidate for developing phase-change random access memories (PCRAMs). The rapid scaling of NVMs, with process nodes below 19nm, and the use of multi-level cell (MLC) technologies has increased their storage density and reduced the storage cost per bit. However, their lifetime capacity has not remained unaffected. Different interferences and noise sources along with aging effects have now a great impact on the reliability and endurance of these memory technologies, and hence, on the storage systems where these memories are used (SSDs, PCRAMs). Numerous techniques, such as wear-leveling, specialized error correcting codes (ECC) and precoding techniques have been employed to compensate these effects, while others, more complex but also more efficient, like dynamic adaptation of read reference thresholds, are at an experimental level. The development of these techniques is based on experimental characterization of NVM cells and chips. Characterization is related with measuring bit error ratio (BER) and response time (read and write time) during the whole lifetime of a device, for various loading data patterns and timing scenarios. This process is performed using real NVM integrated chips, usually the engineering, pre-production parts, while more thorough testing at the system level is performed when production parts are available. This approach has two major drawbacks. On one hand it is a very time-consuming process, since the aging of an NVM may require a large number of program/erase (P/E) cycles to be performed for each experiment, ranging from tens of thousands (NAND Flash) to millions (PCM) program cycles. On the other hand, the aging characteristics of an NVM are proportionally dependent on the number of the performed P/E cycles, thus making it impossible to conduct different or successive experiments at the same aging state of a memory chip. In this work, we present a model that accurately represents the aging process of an NVM cell, by treating it as a time-variant communications channel, based on an asymmetric n-PAM model. We present the architecture of a flexible FPGA-based platform, designed for accurate emulations of NVM technologies, focusing mainly on MLC NAND Flash technologies. Accuracy is measured in reference to experimentally specified bit error probabilities for various aging conditions (ie. the number of P/E cycles applied to a NAND Flash chip), usually for random data patterns. The hardware platform presented in this work is based on a reconfigurable hardware-software architecture, which enables the accurate emulation of new and emerging models and technologies of NVMs. The developed platform can be a valuable tool for the evaluation of memory-related algorithms, signal processing and coding techniques.

Non-volatile memory technologies (NVM) introduce a novel class of devices that combine characteristics of both storage and main memory. Like storage, NVM is not only persistent, but also denser and cheaper than DRAM. Like DRAM, NVM is byte-addressable and has lower access latency. In recent years, NVM has gained a lot of attention both in academia and in the data management industry, with views ranging from skepticism to over excitement. Some critics claim that NVM is not cheap enough to replace flash-based SSDs nor is it fast enough to replace DRAM, while others see it simply as a storage device. Supporters of NVM have observed that its low latency and byte-addressability requires radical changes and a complete rewrite of storage management architectures. This thesis takes a moderate stance between these two views. We consider that, while NVM might not replace flash-based SSD or DRAM in the near future, it has the potential to reduce the gap between them. Furthermore, treating NVM as a regular storage media does not fully leverage its byte-addressability and low latency. On the other hand, completely redesigning systems to be NVM-centric is impractical. Proposals that attempt to leverage NVM to simplify storage management result in completely new architectures that face the same challenges that are already well-understood and addressed by the traditional architectures. Therefore, we take three common storage management architectures as a starting point, and propose incremental changes to enable them to better leverage NVM. First, in the context of log-structured merge-trees, we investigate the impact of storing data in NVM, and devise methods to enable small granularity accesses and NVM-aware caching policies. Second, in the context of B+Trees, we propose to extend the buffer pool and describe a technique based on the concept of optimistic consistency to handle corrupted pages in NVM. Third, we employ NVM to enable larger capacity and reduced costs in a index+log key-value store, and combine it with other techniques to build a system that achieves low tail latency. This thesis aims to describe and evaluate these techniques in order to enable storage management architectures to leverage NVM and achieve increased performance and lower costs, without major architectural changes.:1 Introduction 1.1 Non-Volatile Memory 1.2 Challenges 1.3 Non-Volatile Memory & Database Systems 1.4 Contributions and Outline 2 Background 2.1 Non-Volatile Memory 2.1.1 Types of NVM 2.1.2 Access Modes 2.1.3 Byte-addressability and Persistency 2.1.4 Performance 2.2 Related Work 2.3 Case Study: Persistent Tree Structures 2.3.1 Persistent Trees 2.3.2 Evaluation 3 Log-Structured Merge-Trees 3.1 LSM and NVM 3.2 LSM Architecture 3.2.1 LevelDB 3.3 Persistent Memory Environment 3.4 2Q Cache Policy for NVM 3.5 Evaluation 3.5.1 Write Performance 3.5.2 Read Performance 3.5.3 Mixed Workloads 3.6 Additional Case Study: RocksDB 3.6.1 Evaluation 4 B+Trees 4.1 B+Tree and NVM 4.1.1 Category #1: Buffer Extension 4.1.2 Category #2: DRAM Buffered Access 4.1.3 Category #3: Persistent Trees 4.2 Persistent Buffer Pool with Optimistic Consistency 4.2.1 Architecture and Assumptions 4.2.2 Embracing Corruption 4.3 Detecting Corruption 4.3.1 Embracing Corruption 4.4 Repairing Corruptions 4.5 Performance Evaluation and Expectations 4.5.1 Checksums Overhead 4.5.2 Runtime and Recovery 4.6 Discussion 5 Index+Log Key-Value Stores 5.1 The Case for Tail Latency 5.2 Goals and Overview 5.3 Execution Model 5.3.1 Reactive Systems and Actor Model 5.3.2 Message-Passing Communication 5.3.3 Cooperative Multitasking 5.4 Log-Structured Storage 5.5 Networking 5.6 Implementation Details 5.6.1 NVM Allocation on RStore 5.6.2 Log-Structured Storage and Indexing 5.6.3 Garbage Collection 5.6.4 Logging and Recovery 5.7 Systems Operations 5.8 Evaluation 5.8.1 Methodology 5.8.2 Environment 5.8.3 Other Systems 5.8.4 Throughput Scalability 5.8.5 Tail Latency 5.8.6 Scans 5.8.7 Memory Consumption 5.9 Related Work 6 Conclusion Bibliography A PiBench

Nanokristalle werden beispielsweise für eine Anwendung in Solarzellen, Lichtemittern und nichtflüchtigen Datenspeichern diskutiert. Damit diese Anwendungen funktionieren können, ist eine genaue Kontrolle der Kristallitgröße sowie der Flächendichte und Lage der Kristallite in der Matrix wichtig. Zudem sollte die Matrix amorph sein, da amorphe Matrixmaterialien die Nanokristall-Oberfläche besser passivieren und beständiger gegen Leckströme sind. In dieser Arbeit werden Ge-Nanokristalle in die Hoch-Epsilon-Dielektrika ZrO2 und TaZrOx eingebettet. Im System Ge/ZrO2 kristallisieren die Ge-Cluster und die ZrO2-Matrix bei der gleichen Temperatur. Aufgrund der kristallinen Matrix weicht die Form der Ge-Nanokristalle von einer Kugel ab, worunter unter anderem die Größenkontrolle leidet. Die Beimischung von Ta2O5 stabilisiert die amorphe Phase des ZrO2 und verhindert dadurch die gemeinsame Kristallisation. Dadurch wird es im System Ge/TaZrOx möglich, kugelförmige Ge-Nanokristalle im Größenbereich von 3 nm bis 6 nm positionskontrolliert in eine amorphe Matrix einzubetten. Für die Untersuchung einer möglichen Anwendung des Materialsystems wurden Speicherzellen eines nichtflüchtigen Datenspeichers auf Basis von Ge-Nanokristallen hergestellt. Dabei zeigte sich, dass das System Ge/TaZrOx überdurchschnittlich viele Ladungen speichert und daher für diese Anwendung vielversprechend ist. Zudem stabilisiert die Beimischung von Ta2O5 eine extrem seltene orthorhombische Modifikation des ZrO2. Für ferroelektrische Datenspeicher könnte diese Phase eine aussichtsreiche Alternative zum HfO2 sein.

Modern main memory is primarily built using dynamic random access memory (DRAM) chips. As DRAM chip scales to higher density, there are mainly three problems that impede DRAM scalability and performance improvement. First, DRAM refresh overhead grows from negligible to severe, which limits DRAM scalability and causes performance degradation. Second, although memory capacity has increased dramatically in past decade, memory bandwidth has not kept pace with CPU performance scaling, which has led to the memory wall problem. Third, DRAM dissipates considerable power and has been reported to account for as much as 40% of the total system energy and this problem exacerbates as DRAM scales up. To address these problems, 1) we propose Rank-level Piggyback Caching (RPC) to alleviate DRAM refresh overhead by servicing memory requests and refresh operations in parallel; 2) we propose a high performance and bandwidth efficient approach, called SELF, to breaking the memory bandwidth wall by exploiting die-stacked DRAM as a part of memory; 3) we propose a cost-effective and energy-efficient architecture for hybrid memory systems composed of high bandwidth memory (HBM) and phase change memory (PCM), called Dual Role HBM (DR-HBM). In DR-HBM, hot pages are tracked at a cost-effective way and migrated to the HBM to improve performance, while cold pages are stored at the PCM to save energy.

During recent years the thickness of the gate oxide has been reduced considerably. The progressive miniaturization of devices has caused several phenomena to emerge such as quasi-breakdown, direct tunneling and stress induced leakage currents. Such phenomena significantly modify the performance of the scaled-down MOSFETs. As a part of this research work, an effort has been made to study the performance and characteristics of the thin Gate oxide for MOSFETs and Tunnel Oxide for Floating Gate (FG) MOS devices. The exponential dependence of tunnel current on the oxide-electric field causes some critical problems in process control. A very good process control is therefore required. This can be achieved by finding out the exact value of F-N tunneling parameter. This research work also is an effort of finding an accurate value for parameter B and its dependence on the oxide thickness as the device are scaled down to a level where the probability of Direct Tunneling mechanism gains more prominence. A fully automated Low Current Measurement workstation with noise tolerance as low as 10-15 A was set up as a part of this research. C-V and I-V curves were analyzed to extract, determine and investigate the oxide thickness dependence of F-N parameter B. For oxide thickness in the range10~13 nm, the parameter B ranged between 260 and 267. Thus it can be said that it is not sensitive to the change in oxide thickness in this range. However it was noticed that for thickness around 7nm wide variety of results were obtained for the Fowler-Nordheim parameter B (B ranged from 260 to 454). This can be attributed to the enhancement in the leakage current due to the direct tunneling. Hence to have tight control over VT for a NVM, new algorithms need to be developed for even better process control for oxide thickness in the range of 7 nm and below.

Recently an effective usage of the chip area plays an essential role for System-on-Chip (SOC) designs. Nowadays on-chip memories take up more than 50%of the total die-area and are responsible for more than 40% of the total energy consumption. Cache memory alone occupies 30% of the on-chip area in the latest microprocessors. This thesis project “System Level Exploration of RRAM for SRAM Replacement” describes a Resistive Random Access Memory (RRAM) based memory organizationfor the Coarse Grained Reconfigurable Array (CGRA) processors. Thebenefit of the RRAM based memory organization, compared to the conventional Static-Random Access Memory (SRAM) based memory organization, is higher interms of energy and area requirement. Due to the ever-growing problems faced by conventional memories with Dynamic Voltage Scaling (DVS), emerging memory technologies gained more importance. RRAM is typically seen as a possible candidate to replace Non-volatilememory (NVM) as Flash approaches its scaling limits. The replacement of SRAMin the lowest layers of the memory hierarchies in embedded systems with RRAMis very attractive research topic; RRAM technology offers reduced energy and arearequirements, but it has limitations with regards to endurance and write latency. By reason of the technological limitations and restrictions to solve RRAM write related issues, it becomes beneficial to explore memory access schemes that tolerate the longer write times. Therefore, since RRAM write time cannot be reduced realistically speaking we have to derive instruction memory and data memory access schemes that tolerate the longer write times. We present an instruction memory access scheme to compromise with these problems. In addition to modified instruction memory architecture, we investigate the effect of the longer write times to the data memory. Experimental results provided show that the proposed architectural modifications can reduce read energy consumption by a significant frame without any performance penalty.

This study is focuses on the resistance switching physical mechanism in hafnium oxide (HfO2) of resistive random access memory (RRAM). HfO2 was taken as the resistance switching layer because HfO2 is extremely compatible with the prevalent complementary metal oxide semiconductor (CMOS) process. The detail physical mechanism is studied by the stable RRAM device (Ti/HfO2/TiN), which is offered from Industrial Technology Research Institute (ITRI). In this study, the resistance switching property of two different forming conductions are compared, including DC sweeping forming and AC pulse forming. In general, forming is a pivotal process in resistance random access memory (RRAM) to activate the resistance switching behavior. However, over forming would lead to device damage. The overshoot current has been considered as a degradation reason during the forming process. The circuit design is used to obtain the overshoot effect of DC sweeping forming by oscilloscope and semiconductor parameter analyzer system. The quantity of charge through the switching layer has been proven as the key element in the formation of the conduction path. Ultra-fast pulse forming can form a discontinuous conduction path to reduce the operation power.

L’accroissement du champ d’application et de la performance des microcontrôleurs s’accompagne d’une augmentation de la puissance consommée limitant l’autonomie des systèmes nomades (smartphones, tablettes, ordinateurs portables, implants biomédicaux, …). L’étude menée dans le cadre de la thèse, consiste à réduire la consommation dynamique des circuits fabriqués en technologie CMOS 80 nm avec mémoire non-volatile embarquée (e-NVM) ; à travers l’amélioration des performances des transistors MOS. Pour augmenter la mobilité des porteurs de charge, des techniques de fabrication utilisées dans les nœuds les plus avancés (40 nm, 32 nm) sont d’abord étudiées en fonction de différents critères (intégration, coût, gain en courant/performance). Celles sélectionnées sont ensuite optimisées et adaptées pour être embarquées sur une plate-forme e-NVM 80 nm. L’étape suivante est d’étudier comment transformer le gain en courant, en gain sur la consommation dynamique, sans dégrader la consommation statique. Les approches utilisées ont été de réduire la tension d’alimentation et la largeur des transistors. Un gain en consommation dynamique supérieur à 20 % est démontré sur des oscillateurs en anneau et sur un circuit numérique conçu avec près de 20 000 cellules logiques. La méthodologie appliquée sur le circuit a permis de réduire automatiquement la taille des transistors (évitant ainsi une étape de conception supplémentaire). Enfin, une dernière étude consiste à optimiser la consommation, les performances et la surface des cellules logiques à travers des améliorations de conception et une solution permettant de réduire l’impact de la contrainte induite par l’oxyde STI. / The increase of the scope of application and the performance of microcontrollers is accompanied by an increase in power consumption reducing the life-time of mobile systems (smartphones, tablets, laptops, biomedical implants, …). Here, the work consists of reducing the dynamic consumption of circuits manufactured in embedded non-volatile memories (e-NVM) CMOS 80 nm technology by improving the performance of MOS transistors. In order to increase the carriers’ mobility, manufacturing techniques used in the most advanced technological nodes (40 nm, 32 nm) are firstly studied according to different criteria (process integration, cost, current/performance gain). Then, selected techniques are optimized and adapted to be used on an e-NVM technological platform. The next step is to study how to transform the current gain into dynamic power gain without impacting the static consumption. To do so, the supply voltage and the transistor widths are reduced. Up to 20 % in dynamic current gain is demonstrated using ring oscillators and a digital circuit designed with 20,000 standard cells. The methodology applied on the circuit allows automatic reduction to all transistor widths without additional design modifications. Finally, a last study is performed in order to optimize the consumption, the performance and the area of digital standard cells through design improvements and by reducing the mechanical stress of STI oxide.

Nanokristalle werden beispielsweise für eine Anwendung in Solarzellen, Lichtemittern und nichtflüchtigen Datenspeichern diskutiert. Damit diese Anwendungen funktionieren können, ist eine genaue Kontrolle der Kristallitgröße sowie der Flächendichte und Lage der Kristallite in der Matrix wichtig. Zudem sollte die Matrix amorph sein, da amorphe Matrixmaterialien die Nanokristall-Oberfläche besser passivieren und beständiger gegen Leckströme sind. In dieser Arbeit werden Ge-Nanokristalle in die Hoch-Epsilon-Dielektrika ZrO2 und TaZrOx eingebettet. Im System Ge/ZrO2 kristallisieren die Ge-Cluster und die ZrO2-Matrix bei der gleichen Temperatur. Aufgrund der kristallinen Matrix weicht die Form der Ge-Nanokristalle von einer Kugel ab, worunter unter anderem die Größenkontrolle leidet. Die Beimischung von Ta2O5 stabilisiert die amorphe Phase des ZrO2 und verhindert dadurch die gemeinsame Kristallisation. Dadurch wird es im System Ge/TaZrOx möglich, kugelförmige Ge-Nanokristalle im Größenbereich von 3 nm bis 6 nm positionskontrolliert in eine amorphe Matrix einzubetten. Für die Untersuchung einer möglichen Anwendung des Materialsystems wurden Speicherzellen eines nichtflüchtigen Datenspeichers auf Basis von Ge-Nanokristallen hergestellt. Dabei zeigte sich, dass das System Ge/TaZrOx überdurchschnittlich viele Ladungen speichert und daher für diese Anwendung vielversprechend ist. Zudem stabilisiert die Beimischung von Ta2O5 eine extrem seltene orthorhombische Modifikation des ZrO2. Für ferroelektrische Datenspeicher könnte diese Phase eine aussichtsreiche Alternative zum HfO2 sein.