This thesis explores a rigorous approach to model the behaviour of an electrochemical cell. A simple planar electrochemical cell consisting of stainless steel electrodes separated by a sulfuric acid electrolyte layer is modeled from first principles. The model is a dynamic model and is valid under constant temperature conditions. The dynamic model is based on the Poisson-Nernst-Planck electrodiffusion theory and physical attributes such as the impact of nonlinear polarization, the stoichiometric reactions of the electrolyte and changes to the transport coefficients are investigated in stages. The system of partial differential equations has been solved using a finite element software package. The simulation results are compared with experimental results and discrepancies are discussed. The results suggest that the existing theory is not adequate in explaining the physics in the immediate vicinity of the electrode/electrolyte interface even though the general experimental and simulation results are in qualitative agreement with each other.

A novel, variable-gain switched-capacitor DC-DC converter is designed, constructed and tested. The proposed converter minimizes many of the problems which have traditionally hindered switched-capacitor DC-DC converters. The converter has high efficiency, strong regulation and low output voltage ripple across a wide variation in the line and load. The converter utilizes an optimized switching configuration that contains the maximum number of ideal conversion ratios for the given number of capacitors driven by a two-phase clock. The switched-capacitor converter is controlled by a gain-hopping feedforward control scheme in conjunction with duty-cycle, pulse-width modulation feedback control. The proposed control technique enhances the efficiency and regulation capability of switched-capacitor DC-DC converters, which are typically limited when there is a large variation in the line. Because the converter is optimized, programmable and capable of providing buck and/or boost operation (stepping-up and/or stepping-down the input voltage), the new switched-capacitor DC-DC converter is well-suited for a variety of applications and operating conditions. In addition, a novel algorithm based on graph theory and network analysis is developed which enumerates all possible ideal conversion ratios for a given switched-capacitor DC-DC converter structure. In particular, this algorithm can be used as a design tool to greatly improve the operation of multi-gain switched-capacitor converters, where the aim is to maximize the number of ideal conversion ratios while minimizing the number of switches and capacitors. Furthermore, the structure of all attainable positive, ideal conversion ratios of a two-phase switched-capacitor DC-DC converter, utilizing up to five capacitors, is enumerated. As a result, the design process for switched-capacitor converters is greatly simplified and a suitable converter structure can be more easily selected for a given application. / Thesis (Master, Electrical & Computer Engineering) -- Queen's University, 2013-04-03 23:27:24.183

With superior longevity, approximately 5 times that of compact fluorescents (CFLs), and high efficacy, around 1.5 times that of CFLs, LEDs are now attracting vast attention from both academic and industrial sectors. Unfortunately, current power supply drivers for LEDs have the following drawbacks: (1) for a two-stage configuration, the power factor correction (PFC) circuit can help LEDs achieve good operating performance but contain too many components and are large in size, have low efficiency and relatively high cost; (2) a single-stage configuration can perform well in PFC and efficiency, however reliability issues occur due to the use of the electrolytic capacitor. In this thesis, the theoretical analysis and implementation of two high power factor, soft-switched, electrolytic-capacitor-less LED drivers are presented. The two drivers solve the aforementioned issues while minimizing its size and cost. The detailed theoretical analysis illustrates the advantages of the presented circuits and provides insight into their design and operation. The simulated and experimental implementations verified the performance of both circuits, which achieve a high power factor, indicating that the drivers have good operating performance. Elimination of the electrolytic capacitors improves the LED drivers’ reliability. In addition, with the help of soft-switching capability, high efficiency is achieved. Simulation and experimental results are presented to support all merits of the two circuits. / Thesis (Master, Electrical & Computer Engineering) -- Queen's University, 2013-04-30 13:22:28.471

The aluminum electrolytic capacitor is used extensively in the electric utility industry. A factor limiting the storage of spare capacitors is the integrity of the aluminum oxide dielectric, which over time breaks down contributing to a shelf life currently estimated at one nuclear power electric generating station to be approximately five years. This project examined the electrical characteristics of naturally aged capacitors of several different styles to determine if design parameters were still within limits. Additionally, the effectiveness of a technique known as “Reforming” was examined to determine its impact on those characteristics.

Approved for public release / This research was part of an ongoing program studying the concept of multi-material dielectrics (MMD) with dielectric constants much higher than homogenous materials. MMD described in this study have dielectric constants six orders of magnitude greater than the best single materials. This is achieved by mixing conductive particles with an insulating surface layer into a composite matrix phase composed of high surface area ceramic powder and aqueous electrolyte. Specifically examined in this study was micron-scale nickel powder treated in hydrogen peroxide (H2O2) loaded into high surface area alumina powder and aqueous boric acid solution. This new class of dielectric, composite electrolyte dielectrics (CED), is employed in an electrostatic capacitor configuration and demonstrated dielectric constant of order 10 [raised to the 10th power] at approximately 1 Volt. Additionally, it is demonstrated that treated nickel can be loaded in high volume fractions in the CED configuration. Prior studies of composite capacitors indicated a general limitation due to shorting. This results from the onset of percolation due to excess loading of conductive phases. Insulated particles described herein are successfully loaded up to 40% by volume, far above typical percolation thresholds. Simple models are presented to explain results. / Lieutenant, United States Navy

M.Phil. / The Motraco transmission system is a classical case illustrating the increase in power transfer of a network considering the possibility of a voltage collapse. This case study was used in the dissertation to find a techno-economical solution for the Motraco system to increase the power transfer to satisfy an additional load. The Motraco power system is operating close to a voltage collapse at present. A voltage collapse will be experienced if additional load is added at the Maputo substation. The possibility of a voltage collapse can be reduced if the power transfer capability of the Motraco power system is increased. Various technologies can be used to increase the power transfer of the Motraco power system. The technologies used in this study to increase the power transfer were limited to the following: • Adding shunt capacitor banks at critical locations in the network • Adding a series capacitor bank on an existing 400 kV transmission line • Adding an additional 400 kV transmission line • Adding a series capacitor bank on the new 400 kV transmission line The correct use of the combination of the shunt capacitor banks, series capacitor bank and the new transmission line contributes to: • support voltages in the network; • reduce the transmission losses; and • increase the fault levels at the receiving end. The principles used in this dissertation can be used to increase the power transfer limit of any power system with the same characteristics.

Modern electric power utilities are facing a variety of challenges introduced by the increasing complexity of their operation, structure, and consumer loads. One such challenge has been to supply the ever growing demand for reactive power which is essential for grid support. For this reason dynamic VAR technologies are becoming much more important to modern day power systems. A recent dynamic VAR technology known as the Dynamic Capacitor offers full quadrant capacitive VAR control through the combination of AC/AC buck and boost cells. This paper introduces a new topology deemed the “Four-Switch Buck-Boost Dynamic Capacitor” which promises to combine the performance of the AC/AC buck and boost cells into a single power electronic device. This is done in an effort to reduce the required component count and thus reduce the overall device footprint and implementation cost of the Dynamic Capacitor technology. Derivations and analysis will detail the workings of the Four-Switch Buck-Boost Dynamic Capacitor, while simulations in LTSpice and Matlab Simulink will demonstrate the functionality and performance of the proposed topology. The results of this thesis prove the Four-Switch Buck-Boost Dynamic Capacitor to be a feasible shunt reactive compensating device.

Metallised polypropylene (MPP) capacitors, the dominant capacitor type used in a wide range of power and electronic circuit applications, offer high volumetric capacitor density, low cost, excellent frequency characteristics and a unique ability to recover from point failures in the dielectric film. However MPP capacitors have a generic weakness that is not well understood, failure of the self-healing process leading to ongoing catastrophic failure. The work described in this thesis includes the derivation of an improved electrical model of a capacitor and the uncovering of a mechanism for the catastrophic failure mode. Corrosion of the thin metallic field is firmly linked to drastic increases in metal film current densities and generation of hot spots in capacitors. In the work, novel formulae were derived relating capacitor parameters such as equivalent series resistance and equivalent series capacitance to frequency and physical characteristics such as metal film resistivity and physical dimensions of multiple layer capacitors. Modelling using numerical methods and diffusion equation showed that capacitors with double-end connection topology have more uniform voltage and power distribution than single-end connected capacitors. External characteristics of both connection topologies were shown to be virtually identical up to frequencies well above typical self-resonance. The aggregate spatial distribution of power from both layers and the voltage across the dielectric were found to be fundamentally different in the two circuit connection topologies. In this work it was shown that above singularity frequencies defined by distributed capacitance and metal film spreading resistance, equivalent series resistance and capacitance both fall with the square root of frequency Analysis of the inductance of typical MPP capacitors for single-end and double-end connected topologies and for circumferentially connected capacitor metallization showed that the magnitude and effect of distributed inductance in typical MPP power capacitors was insignificant compared to packaging inductance. Thermal and electrical modelling and experimental measurements showed that corrosion effects could readily account for the generic catastrophic failure mode of metallised polypropylene capacitors. Modelling showed that remnant vestiges of metal bridging corrosion gaps between the schooping and the metallic film could also pose serious thermal danger to the affected capacitor. Fusing current modelling and experimental measurement showed that fusing in metallic films typically occurred for current densities of several hundred thousand amperes per square centimetre. The partial disconnection of the metallic layers from the schooping edge by corrosion for example, was shown to result in large increases in dissipation factor and power loss in a capacitor readily explaining how capacitors

Pipelined analog to digital converters (ADCs) are very important building blocks in many electronic systems such as high quality video systems, high performance digital communication systems and high speed data acquisition systems. The rapid development of these applications is driving the design of pipeline ADCs towards higher speed, higher dynamic range, lower power consumption and lower power supply voltage with the CMOS technology scaling. This trend poses great challenges to conventional pipelined ADC designs which rely on high-gain operational amplifiers (opamps) and well matched capacitors to achieve high accuracy. In this thesis, two novel accuracy improvement techniques to overcome the accuracy limit set by analog building blocks (opamps and capacitors) in the context of low-voltage and high-speed pipelined ADC design are presented. One is the time-shifted correlated double sampling (CDS) technique which addresses the finite opamp gain effect and the other is the radix-based background digital calibration technique which can take care of both finite opamp gain and capacitor mismatch. These methods are simple, easy to implement and power efficient. The effectiveness of the proposed techniques is demonstrated in simulation as well as in experiment. Two prototype ADCs have been designed and fabricated in 0.18μm CMOS technology as the experimental verification of the proposed techniques. The first ADC is a 1.8V 10-bit pipeline ADC which incorporated the time-shifted CDS technique to boost the effective gain of the amplifiers. Much better gain-bandwidth tradeoff in amplifier design is achieved with this gain boosting. Measurement results show total power consumption of 67mW at 1.8V when operating at 100MSPS. The SNR, SNDR and SFDR are 55dB, 54dB and 65dB respectively given a 1MHz input signal. The second one is a 0.9V 12-bit two-stage cyclic ADC which employed a novel correlation-based background calibration to enhance the linearity. The linearity limit set by the capacitor mismatches, finite opamp gain effects is exceeded. After calibration, the SFDR is improved by about 33dB and exceeds 80dB. The power consumption is 12mW from 0.9V supply when operating at 2MSPS. / Graduation date: 2004

Switched-capacitor (SC) circuits are commonly used for analog signal processing because they can be used to realize precision filters and data converters on an integrated circuit (IC). However, for high speed applications SC circuit operating speeds are limited by the internally-compensated opamps found in SC integrators, a common building block of these circuits. This thesis studies gain stages that eliminate the internal compensation, thus allowing the SC circuits to operate at significantly higher operating speeds. An inverter-based SC integrator is presented. The proposed SC integrator is built with a pseudo-differential structure to improve its rejection of common-mode noise, such as charge injection and clock feedthrough. The proposed integrator also incorporates correlated double sampling (CDS) to boost its effective DC gain. Clock-boosting and switch bootstrapping techniques are not used in the proposed circuit, even though it uses a low supply voltage. To verify the speed advantage of the proposed circuit, a high speed delta sigma (Δ∑) modulator was designed in a 1.8V, 0.18μm CMOS technology. The designed Δ∑ modulator operates at a clock frequency of 500MHz. Circuit implementation and layout floorplan are described. The design is based on MATLAB and SpectreS simulations. / Graduation date: 2002