In recent high-speed digital circuits, the simultaneous switching noise (SSN) or ground bounce noise (GBN) is induced due to the transient currents flowing between power and ground planes during the state transitions of the logic gates. In order to¡@analyze the effect of GBN on power delivery systems effectively and accurately, the impedance of power/ground is an important index to evaluate power delivery systems. In the operating frequency bandwidth, the power impedance must be less than the target impedance. The typical way to suppress the SSN is adding decoupling capacitors to create a low impedance path between power and ground planes. By using the admittance matrix method, we can evaluate the effect of decoupling capacitors mounted on PCB fast and accurately reducing the time needed from the empirical or try-and-error design cycle. In order to reduce the cost of decoupling capacitors, the genetic algorithm is employed to optimize the placement of decoupling capacitors to suppress the GBN. The decoupling capacitor are not effective in the GHz frequency range due to their inherent lead inductance. The electromagnetic bandgap(EBG) structure can produce a stopband to prevent the noise from disperseing at higher frequency. Combining decoupling capacitors with EBG structure to find the optimum placement for suppression of the SSN by using the genetic algorithm.

A new DC-DC up converter with high efficiency and low output ripple is proposed. We replace previous charge pump converters by switched-capacitor converters to improve the power efficiency and add a voltage regulator at the output to reduce the ripple voltage. The converter reduces the magnitude of output voltage ripples to 36% of the previous converter, and improves the power efficiency from 58% to 73%. The proposed converter is designed to obtain 1.6 mA driving capability with a output voltage around 5.3 ~ 5.4 V. A VCO is also added as the load to test the converter circuit. The VCO is insensititive to power supply noises. The proposed converter circuit is simulated in a TSMC 0.35-um Mixed-mode (2P4M) CMOS process.

This thesis investigates the various techniques to achieve large time constants and the ultimate limitations therein. A novel circuit technique for the realization of large time constants for high pass corners in switched-capacitor filters is also proposed and compared with existing techniques. The switched-capacitor technique is insensitive to parasitic capacitances and is area efficient and it requires only two clock phases. The circuit is used to build a typical switched-capacitor front end with a gain of 10. The low pass corner is fixed at 200 Hz. The high pass corner is varied from 0.159Hz to 4 Hz and various performance parameters, such as power consumption, silicon area etc., are compared with conventional techniques and the advantages and disadvantages of each technique are demonstrated. The front-ends are fully differential and are chopper stabilized to protect against DC offsets and 1/f noise. The front-end is implemented in AMI0.6um technology with a supply voltage of 1.6V and all transistors operate in weak inversion with currents in the range of tens of nano-amperes.

This work presents design techniques for the implementation of high-speed analog integrated circuits for wireless and wireline communications systems. Limitations commonly found in high-speed switched-capacitor (SC) circuits used for intermediate frequency (IF) filters in wireless receivers are explored. A model to analyze the aliasing effects due to periodical non-uniform individual sampling, a technique used in high-Q high-speed SC filters, is presented along with practical expressions that estimate the power of the generated alias components. The results are verified through circuit simulation of a 10.7MHz bandpass SC filter in TSMC 0.35mu-m CMOS technology. Implications on the use of this technique on the design of IF filters are discussed. To improve the speed at which SC networks can operate, a continuous-time common-mode feedback (CMFB) with reduced loading capacitance is proposed. This increases the achievable gain-bandwidth product (GBW) of fully-differential ampli- fiers. The performance of the CMFB is demonstrated in the implementation of a second-order 10.7MHz bandpass SC filter and compared with that of an identical filter using the conventional switched-capacitor CMFB (SC-CMFB). The filter using the continuous-time CMFB reduces the error due to finite GBW and slew rate to less than 1% for clock frequencies up to 72MHz while providing a dynamic range of 59dB and a PSRR- > 22dB. The design of high-speed transversal equalizers for wireline transceivers requires the implementation of broadband delay lines. A delay line based on a third-order linear-phase filter is presented for the implementation of a fractionally-spaced 1Gb/s transversal equalizer. Two topologies for a broadband summing node which enable the placement of the parasitic poles at the output of the transversal equalizer beyond 650MHz are presented. Using these cells, a 5-tap 1Gb/s equalizer was implemented in TSMC 0.35mu-m CMOS technology. The results show a programmable frequency response able to compensate up to 25dB loss at 500MHz. The eye-pattern diagrams at 1Gb/s demonstrate the equalization of 15 meters and 23 meters of CAT5e twistedpair cable, with a vertical eye-opening improvement from 0% (before the equalizer) to 58% (after the equalizer) in the second case. The equalizer consumes 96mW and an area of 630mu-m x 490mu-m.

The passive devices used in the wireless communication system ¡]including resistor, capacitor and inductor¡^usually need high quality factor and low power dissipation characteristics. This thesis aims to develop a micro tunable capacitor with high-quality-factor and wide-tuning-range using surface micromachining. In contrast with conventional low-tuning-rate parallel-plate tunable capacitors, this research presents a concave structure and eight-suspending-beams layout design of the top electrode to enhance the elastic rigidity and tuning rate. In addition, this study appropriately decreases the thickness of top electrode, the tuning rate of such device can be improved to 65~2100%. On the other hand, in order to substantially increase quality factor, this thesis adopted the glass substrate ¡]Corning 7740¡^to reduce the power dissipation of high frequency operating signal. The optimized quality factor of this work is approximately equal to 41 under 2.4 GHz operation frequency. The material of sacrificial layer and top electrode adopted in this dissertation is aluminum and gold respectively. To avoid any breakage of the vertical supporting beams during releasing process, this research appropriately increases the width of vertical supporting beams, however, keep the thickness of the suspending part of top electrode for the maintenance of high quality factor and low driving voltage.

Title from PDF of title page (University of Missouri--Columbia, viewed on March 10, 2010). The entire thesis text is included in the research.pdf file; the official abstract appears in the short.pdf file; a non-technical public abstract appears in the public.pdf file. Thesis advisor: Dr. Robert M O'Connell. Includes bibliographical references.

The objective of this thesis is to determine a method for computing the amount of capacitance in a power electronic converter required to melt a fuse in the event of a line to ground fault. DC micro-grids rely on power electronic converters to change voltage levels. All converters rely on semiconductor switches that must be protected from surges of fault current. This limits the power that a converter can supply to a fuse. In many cases, sufficient power may be achieved by appropriately sizing the converters’ output capacitor. / text

This work examines the role of charge redistribution in the self-discharge of electrochemical capacitor electrodes. Electrochemical capacitors are charge storage devices which have high power capability and a long cycle life, but have a low energy density compared to other devices, coupled with a high rate of self-discharge which further diminishes the available energy. The mechanisms of self-discharge in electrochemical capacitors are poorly understood, and it is important to gain a better understanding of the electrode processes which lead to self-discharge, in order to minimize self-discharge and enhance electrochemical capacitor performance. To learn more about charge redistribution and its role in the self-discharge of electrochemical capacitors, multiple self-discharge experiments were performed on carbons with various surface areas/pore structures and in various electrolytes. Charge redistribution was also examined in a model pore (a transmission line circuit based on de Levie?s model of a porous electrode) and results from this model were compared to the self-discharge of a high surface-area carbon. Results demonstrate that charge redistribution is a major component of the self-discharge in high surface-area carbons. Results also indicate that charge redistribution requires a much longer time than previously thought (tens of hours rather than minutes) which further highlights the importance of charge redistribution during self-discharge. Therefore when performing mechanistic studies of self-discharge in electrochemical capacitors, it is important that effects of charge redistribution are not neglected. The self-discharge profiles of various pore shapes were also examined using the model pore, and results emphasize the superiority of cone and cylindrically shaped pores, and the disadvantages of restrictive pore mouths and bottlenecks for high power applications.

A low-noise, variable gain amplier chain was constructed for interfa-cing a sensor to an ADC. During the course of the work two dierent methods -switched-capacitor circuits and chopping circuits - for dealing with 1/f noise wereinvestigated during the course of the work. The resulting circuit did not quitemeet the performance required by the specication, some possible improvementsare suggested.

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