Recently, switched capacitor DC/DC converters are extensively used in portable electronic devices because they feature many advantages, such as high efficiency, small package, low quiescent current, minimal external components and low cost. In this thesis, two step-down switched capacitor DC/DC converters are designed. One has the fixed output options 1.5V, 1.8V and 2.0V. The other one has the output 1.2V. These two converters are implemented in 0.5��m CMOS process through National Semiconductor Corporation. The design is verified by the circuit-level simulations, and design issues are discussed. / Graduation date: 2004

This thesis describes compensation techniques for cascaded delta-sigma A/D converters (ADCs) and high-performance switched-capacitor (SC) circuits. Various correlated-double-sampling (CDS) techniques are presented to reduce the effects of the nonidealities, such as clock feedthrough, charge injection, opamp input-referred noise and offset, and finite opamp gain, in SC circuits. A CDS technique for the compensation of opamp input-referred offset and clock-feedthrough effect is examined and improved to achieve continuous operation. Experimental results show that after the compensation, the SC integrator's output signal swing is greatly increased. The effects of the analog circuitry nonidealities in delta-sigma ADCs are also analyzed. The analysis shows that the nonidealities in cascaded delta-sigma ADCs cause noise leakage, which limits the overall performance of the cascaded modulators. In order to reduce the noise leakage, a novel adaptive compensation technique is proposed. To verify the effectiveness of the proposed compensation techniques, a prototype 2-0 cascaded modulator was designed. Its first stage, a second-order delta-sigma modulator with test signal input circuit, was designed and fabricated in 1.2 ��m CMOS technology. The measurement results show that the noise leakage is reduced effectively by the compensation, and the performance of the cascaded delta-sigma modulator is greatly improved. / Graduation date: 1999

Thesis (M.S.)--Oregon State University, 2007. / Printout. Includes bibliographical references (leaves 82-86). Also available on the World Wide Web.

This thesis investigates the various techniques to achieve large time constants and the ultimate limitations therein. A novel circuit technique for the realization of large time constants for high pass corners in switched-capacitor filters is also proposed and compared with existing techniques. The switched-capacitor technique is insensitive to parasitic capacitances and is area efficient and it requires only two clock phases. The circuit is used to build a typical switched-capacitor front end with a gain of 10. The low pass corner is fixed at 200 Hz. The high pass corner is varied from 0.159Hz to 4 Hz and various performance parameters, such as power consumption, silicon area etc., are compared with conventional techniques and the advantages and disadvantages of each technique are demonstrated. The front-ends are fully differential and are chopper stabilized to protect against DC offsets and 1/f noise. The front-end is implemented in AMI0.6um technology with a supply voltage of 1.6V and all transistors operate in weak inversion with currents in the range of tens of nano-amperes.

The core of any electric vehicle (EV) is the electric drive train, intended as the energy conversion chain from the energy tank (typically some kind of rechargeable battery) to the electric motor that converts the electrical energy into the mechanical energy needed for the vehicle motion. The need for on-board electrical energy storage is the factor that has so far prevented pure electric vehicles from conquering significant market share. In fact electrochemical batteries, which are currently the most suitable device for electrical energy storage, have serious limitations in terms of energy and/or power density, cost and safety. All those characteristics reflect in pure electric vehicles being outperformed by standard internal combustion engine (ICE) based vehicles in terms of driving range, time needed to refuel and purchase cost. Electric vehicles do have their distinctive advantages, being intrinsically much more efficient, operating at zero emissions at the pipe, and offering a higher degree of controllability that can potentially enhance driving safety. No wonder then, that electric energy storage technology has attracted considerable R&D investments, resulting in new traction battery packs that are getting closer and closer to the industrial targets. In this scenario of EV technology gaining momentum, power electronics engineers have to come up with newer solutions allowing for more efficient and more reliable utilization of the precious on-board energy that comes in a form that cannot be directly utilized by the motor. At present, most of the research in the area of power electronics for automotive is focused in volume and cost reduction techniques. The increase in power density is pursued by developing components that can be operated at higher temperature, thus relieving the requirements on cooling. In this thesis, the focus is on the development of alternative topologies for the power electronics converters that make use of some peculiarities of the energy storage components and of the electrical drive train in general, rather than being a mere component-level optimization of well established topologies. A novel converter topology is proposed for hybridization of the energy source with a supercapacitor-based power buffer being used to assist the main traction battery. From the functional point of view, the topology implements a bidirectional DC/DC converter. Making use of the fact that the battery terminal voltage is close to constant, an arrangement for the supercapacitors is devised allowing for bidirectional power flow by using power electronics devices of lower ratings than the ones needed in conventional DC/DC converters. At the same time, much smaller magnetic components are needed. Theoretical analysis of the operation of the proposed converter is given, allowing for optimized design. A full-scale experimental prototype rated at 30 kW, intended for use in a pure EV, has been built and tested. Results validate the theory and show that no particular impediment exist to the deployment of the concept in practical applications. Another concept introduced in the thesis is an architecture where the traction inverter is embedded in the energy storage device. The latter is constituted by several modules, as in the case of modern Li-ion battery systems, and each module is equipped with a local power electronics interface, making it functionally equivalent to a controllable voltage source. The result is a modular, distributed system that can be engineered to have very high reliability and also to exhibit self-healing properties. A prototype with a minimum number of modules has been built and tested. Results confirm the effectiveness of the system, and make it a good candidate for deployment in applications where reliability is the most important requirement.

A hybrid operational amplifier compensation technique using Miller and multipath compensation is presented for multi-stage amplifier designs. Unconditional stability is achieved by the means of pole-zero cancellation where left-half zeros cancel out the non-dominant poles of the operational amplifier. The compensation technique is stable over process, temperature, and voltage variations. Compared to conventional Miller-compensation, the proposed compensation technique exhibits improved settling response for operational amplifiers with the same gain, bandwidth, power, and area. For the same settling time, the proposed compensation technique will require less area and consume less power than conventional Miller-compensation. Furthermore, the proposed technique exhibits improved output slew rate and lower noise over the conventional Miller-compensation technique. Two-stage operational amplifiers were designed in a 0.18µm CMOS process using the proposed technique and conventional Miller-compensated technique. The design procedure for the two-stage amplifier is applicable for higher-order amplifier designs. The amplifiers were incorporated into a switched-capacitor oscillator where the oscillation harmonics are dependent on the settling behaviour of the op amps. The superior settling response of the proposed compensation technique results in a improved output waveform from the oscillator.

The objective of this research is to advance the field of condition monitoring of electrolytic capacitors used in power electronics circuits. The construction process of an electrolytic capacitor is presented. Descriptions of various kinds of faults that can occur in an electrolytic capacitor are discussed. The methods available to detect electrolytic capacitor faults are discussed. The effects of the capacitor faults on the capacitor voltage and current waveforms are investigated through experiments. It is also experimentally demonstrated that faults in the capacitor can be detected by monitoring the capacitor voltage and current. Various ESR estimation based detection techniques available to detect capacitor failures in power electronics circuits are reviewed. Three algorithms are proposed to track and detect capacitor failures: an FFT based algorithm, a system modeling based detection scheme, and finally a parameter estimation based algorithm. The parameter estimation based algorithm is a low-cost real-time scheme, and it is inexpensive to implement. Finally, a detailed study is carried out to understand the failure mechanism of an electrolytic capacitor due to inrush current.

Acquisition of bio-signals is an important feature in advanced medical applications. In order to record bio-signals such as electrocardiogram (ECG) or electromyogram (EMG), a switched-capacitor amplifier with variable linear gain and low noise front-end is discussed in this thesis. The circuit is designed and implemented as an Application-Specific Integrated Circuit (ASIC). This ASIC consists of transconductance stage with custom-designed lateral bipolar transistors in the input stage, switched-capacitor integrating stage, sample-and-hold circuit and buffer output stage. Lateral bipolar transistors were chosen with the intention of reducing flicker noise compared to using MOS input devices. Using a switched-capacitor (SC) stage the gain is adjustable to accommodate input signals of different amplitude making it useful for the recording of different biomedical signals. Adjustable gain is achieved by varying the clock phase delay between two digital control signals which were generated by a microcontroller. Also, small size and low supply voltage operation (¡Ó0.9 V) are achieved. Therefore, this ASIC may be used in wearable or even with implantable medical applications. Measured results for test chips realized in TSMC 0.35 £gm CMOS technology are reported confirming the correct operation of the circuit.

The profound digitization of modern microelectronic modules made Analog-to- Digital converters (ADC) key components in many systems. With resolutions up to 14bits and sampling rates in the 100s of MHz, the pipeline ADC is a prime candidate for a wide range of applications such as instrumentation, communications and consumer electronics. However, while past work focused on enhancing the performance of the pipeline ADC from an architectural standpoint, little has been done to individually address its fundamental building blocks. This work aims to achieve the latter by proposing design techniques to improve the performance of these blocks with minimal power consumption in low voltage environments, such that collectively high performance is achieved in the pipeline ADC. Towards this goal, a Recycling Folded Cascode (RFC) amplifier is proposed as an enhancement to the general performance of the conventional folded cascode. Tested in Taiwan Semiconductor Manufacturing Company (TSMC) 0.18?m Complementary Metal Oxide Semiconductor (CMOS) technology, the RFC provides twice the bandwidth, 8-10dB additional gain, more than twice the slew rate and improved noise performance over the conventional folded cascode-all at no additional power or silicon area. The direct auto-zeroing offset cancellation scheme is optimized for low voltage environments using a dual level common mode feedback (CMFB) circuit, and amplifier differential offsets up to 50mV are effectively cancelled. Together with the RFC, the dual level CMFB was used to implement a sample and hold amplifier driving a singleended load of 1.4pF and using only 2.6mA; at 200MS/s better than 9bit linearity is achieved. Finally a power conscious technique is proposed to reduce the kickback noise of dynamic comparators without resorting to the use of pre-amplifiers. When all techniques are collectively used to implement a 1Vpp 10bit 160MS/s pipeline ADC in Semiconductor Manufacturing International Corporation (SMIC) 0.18[mu]m CMOS, 9.2 effective number of bits (ENOB) is achieved with a near Nyquist-rate full scale signal. The ADC uses an area of 1.1mm2 and consumes 42mW in its analog core. Compared to recent state-of-the-art implementations in the 100-200MS/s range, the presented pipeline ADC uses the least power per conversion rated at 0.45pJ/conversion-step.

Low Dropout Regulators (LDOs) are extensively used in portable applications like mobile phones, PDAs and notebooks. These portable applications demand high power efficiency and low output voltage ripple. In addition to these, the radio circuits in these applications demand high power supply rejection (PSR). The output voltage of a conventional DC/DC converter (generally switched mode) has considerable ripple which feeds as input to these LDOs. And the challenge is to suppress these ripples for wide range of frequencies (for radio units) to provide clean supply. Enhanced buffer based compensation is proposed for the fully on-chip CMOS LDO which stabilizes the loop for different load conditions as well as improve the power supply rejection (PSR) until frequencies closer to open loop‟s unity-gain frequency. The stability and PSR are totally valid even for load capacitor varying from 0 to 100 pF. The proposed capacitor-less LDO is fabricated in On-Semi 0.5 μm fully CMOS process. Experimental results confirm a PSR of -30 dB till 420 KHz for the maximum load current of 50mA. The load transients of the chip shows transient glitches less than 90 mV independent of output capacitance.