Este trabalho propõe uma estratégia para projeto de circuitos VLSI operando em amplo ajuste de tensão e frequência (VFS), desde o regime em Near-threshold, onde uma tensão de VDD caracteriza-se por permitir o funcionamento do circuito com o mínimo dispêndio de energia por operação (MEP), até tensões nominais, dependendo da carga de trabalho exigida pela aplicação. Nesta dissertação é proposto o dimensionamento de transistores para três bibliotecas de células utilizando MOSFETs com tensões de limiar distintas: Regular-VT (RVT), High-VT (HVT) e Low-VT (LVT). Tais bibliotecas possuem cinco células combinacionais: INV, NAND, NOR, OAI21 e AOI22 em múltiplos strengths. A regra para dimensionamento dos transistores das células lógicas foi adaptada de trabalhos relacionados, e fundamenta-se na equalização dos tempos de subida e descida na saída de cada célula, objetivando à redução dos efeitos de variabilidade em baixas tensões de operação. Dois registradores também foram incluídos na biblioteca RVT e sua caracterização foi realizada considerando os parâmetros de processo CMOS 65 nm typical, fast e slow; nas temperaturas de operação de -40°C, 25°C e 125°C, e para tensões variando de 200 mV até 1,2V, para incluir a região de interesse, próxima ao MEP. Os experimentos foram realizados utilizando dez circuitos VLSI de teste: filtro digital notch, um núcleo compatível com o micro-controlador 8051, quatro circuitos combinacionais e quatro sequenciais do benchmark ISCAS. Em termos de economia de energia, operar no MEP resulta em uma redução média de 54,46% em relação ao regime de sub-limiar e até 99,01% quando comparado com a tensão nominal, para a temperatura de 25°C e processo típico. Em relação ao desempenho, operar em regime de VFS muito amplo propicia frequências máximas que variam de centenas de kHz até a faixa de centenas de MHz a GHz, para as temperaturas de -40°C e 25°C, e de MHz até GHz em 125°C. Os resultados desta dissertação, quando comparados a trabalhos relacionados, demonstraram, em média, redução de energia e ganho de desempenho de 24,1% e 152,68%, respectivamente, considerando os mesmos circuitos de teste, operando no ponto de mínima energia (MEP). / This work proposes a strategy for designing VLSI circuits to operate in a very-wide Voltage-Frequency Scaling (VFS) range , from the supply voltage at which the minimum energy per operation (MEP) is achieved, at the Near-Threshold regime, up to the nominal supply voltage for the processes, if so demanded by applications workload. This master thesis proposes the sizing of transistors for three library cells using MOSFETs with different threshold voltages: Regular-VT (RVT), High-VT (HVT), and Low-VT (LVT). These libraries have five combinational cells: INV, NAND, NOR, OAI21, and AOI22 with multiple strengths. The sizing rule for the transistors of the digital cells was an adapted version from related works and it is directly driven by requiring equal rise and fall times at the output for each cell in order to attenuate variability effects in the low supply voltage regime. Two registers were also included in the RVT library cell. This library cell was characterized for typical, fast, and slow processes conditions of a CMOS 65nm technology; for operation at -40ºC, 25ºC, and 125ºC temperatures, and for supply voltages varying from 200 mV up to 1.2V, to include the region of interest, for VDD near the MEP. Experiments were performed with ten VLSI circuit benchmarks: notch filter, 8051 compatible core, four combinational and four sequential ISCAS benchmark circuits. From the energy savings point of view, to operate in MEP results on average reduction of 54.46% and 99.01% when compared with the sub-threshold and nominal supply voltages, respectively. This analysis was performed for 25⁰C and typical process. When considered the performance, the very-wide VFS regime enables maximum operating frequencies varying from hundreds of kHz up to MHz/GHz at -40ºC and 25ºC, and from MHz up to GHz at 125ºC. This master thesis results, when compared with related works, showed on average an energy reduction and performance gain of 24.1% and 152.68%, respectively, for the same circuit benchmarks operating with VDD at the minimum energy point (MEP).

Este trabalho apresenta o projeto de um bloco LNA-Misturador dentro de um mesmo circuito integrado para aplicações em um receptor Bluetooth 2;45GHz. Uma estratégia de projeto bem clara, concisa e com uma boa base física e matemática foi desenvolvida para auxiliar o processo de projeto de um bloco LNA-Misturador, composto por um LNA cascode em cascata com um misturador de chaveamento de corrente com entradas simples e degeneração indutiva nas fontes dos estágios de transcondutância. Esta estratégia foi adaptada de trabalhos apresentados na literatura. A estratégia de projeto proposta considera o compromisso entre ruído, linearidade, ganho, dissipação de potência, casamento de impedâncias e isolamento de portas, usando as dimensões dos dispositivos e condições de polarização como variáveis de projeto. Com base nesta estratégia se obteve um bloco LNA-Misturador que atinge algumas especificações propostas. Um bloco LNA-Misturador foi projetado e fabricado em uma tecnologia CMOS 0;35µm para validar a estratégia de projeto proposta. Além disso, para atingir os objetivos, durante o desenvolvimento deste trabalho foi dada atenção especial no projeto dos indutores. Foi projetado, fabricado e medido um chip de teste. Para tal fim foram aplicadas técnicas e estruturas de de-embedding nas medidas para conseguir resultados mais confiáveis. Os resultados experimentais obtidos para os indutores e os resultados preliminares do bloco LNA-Misturador s~ao satisfatórios de acordo com as especificações e os esperados das simulações. No entanto, os indutores integrados degradam significativamente o desempenho do bloco LNA-Misturador. Se forem usados processos de fabricação nos quais os indutores apresentem melhor desempenho, os resultados do bloco LNA-Misturador aplicando a estratégia de projeto desenvolvida neste trabalho podem ser melhorados. Finalmente, é importante ressaltar que a estratégia de projeto proposta neste trabalho já está sendo usada e adaptada em outros projetos com o propósito de melhorar os resultados obtidos, e conseguir auxiliar o processo de projeto deste tipo de blocos. / This work presents a fully integrated LNA-Mixer design for a Bluetooth receiver application at 2:45GHz. A concise design strategy with good physics and mathematics basis was developed to assist the design process of a LNA-Mixer block, formed by a cascode LNA in cascade to a single balanced current commutation Mixer with inductive degeneration. This strategy was adapted from literature and considers the trade-offs between noise, linearity, gain, power dissipation, impedance matching and ports isolation, using the device dimensions and bias conditions as design variables. Based on this strategy, the proposed LNA-Mixer design specifications were achieved. To validate the proposed design strategy, the LNA-Mixer were fabricated in a 0:35µm CMOS process. Furthermore, to achieve the specifications, during the development of this work a special attention to the RF CMOS inductors was given. A test chip was designed, fabricated and measured applying de-embedding structures to obtain more reliable results. The experimental results obtained for the inductors and the preliminary results for the LNA-Mixer are satisfactory compared to the specifications and as expected from simulations. However, the integrated inductors degrade the performance of the block significantly and if a manufacturing process in which the inductor has better performance is used, the resulting LNA-Mixer design applying the strategy developed in this work can be improved. Finally, it is important to highlight that the design strategy proposed in this work is already being used and adapted in other designs in order to improve the results, and to assist the design process of such blocks.

This thesis presents a novel biomimetic cochlea filter which closely resembles the biological cochlea behaviour. The filter is highly feasible for analogue very-large-scale integration (VLSI) circuits, which leads to a micro-watt-power and millimetre-sized hardware implementation. By virtue of such features, the presented filter contributes to a solid foundation for future biologically-inspired audio signal processors. Unlike existing works, the presented filter is developed by taking direct inspirations from the physiologically measured results of the biological cochlea. Since the biological cochlea has prominently different characteristics of frequency response from low to high frequencies, the biomimetic cochlea filter is built by cascading three sub-filters accordingly: a 2nd-order bandpass filter for the constant gentle low-frequency response, a 2nd-order tunable low-pass filter for the variable and selective centre frequency response and a 5th-order elliptic filter for the ultra-steep roll-off at stop-band. As a proof of concept, a biomimetic cochlea filter bank is built to process audio signals, which demonstrates the highly discriminative spectral decomposition and high-resolution time-frequency analysis capabilities similar to the biological cochlea. The filter has simple representation in the Laplace domain which leads to a convenient analogue circuit realisation. A floating-active-inductor circuit cell is developed to build the corresponding RLC ladder for each of the three sub-filters. The circuits are designed based on complementary metal-oxide-semiconductor (CMOS) transistors for VLSI implementation. Non-ideal factors of CMOS transistors including parasitics, noise and mismatches are extensively analysed and consciously considered in the circuit design. An analogue VLSI chip is successfully fabricated using 0.35μ m CMOS process. The chip measurements demonstrate that the centre frequency response of the filter has about 20 dB wide gain tuning range and a high quality factor reaching maximally over 19. The filter has a 20 dB/decade constant gentle low-frequency tail and an over 300 dB/decade sharp stop-band roll-off slope. The measured results agree with the filter model expectations and are comparable with the biological cochlea characteristics. Each filter channel consumes as low as 59.5 ~90μ Wpower and occupies only 0.9 mm2 area. Besides, the biomimetic cochlea filter chip is characterised from a wide range of angles and the experimental results cover not only the auditory filter specifications but also the integrated circuit design considerations. Furthermore, following the progressive development of the acoustic resonator based on microelectro- mechanical systems (MEMS) technology, a MEMS-CMOS implementation of the proposed filter becomes possible in the future. A key challenge for such implementation is the low sensing capacitance of the MEMS resonator which suffers significantly from sensitivity degradation due to the parasitic capacitance. A novel MEMS capacitive interface circuit chip is additionally developed to solve this issue. As shown in the chip results, the interface circuit is able to cancel the parasitic capacitance and increase the sensitivity of capacitive sensors by 35 dB without consuming any extra power. Besides, the chopper-stabilisation technique is employed which effectively reduces the circuit flicker noise and offsets. Due to these features, the interface circuit chip is capable of converting a 7.5 fF capacitance change of a 1-Volt-biased 0.5 pF capacitive sensor pair into a 0.745 V signal-conditioned output while consuming only 165.2μ W power.

This thesis is based on a paper by V. Issakov, presented 2009, where a circuit of a merged power amplifier mixer solution was demonstrated. This work takes that solution and simplifies it for the use at a lower frequency. The implementation target is a Doppler radar application in CMOS that can detect humans in a range of 5 to 15 meters. This could be used as a burglar alarm or an automatic light switch. The report will present the background of Issakov’s work, basic theory used and the implementation of the final design. Simulations will show that the solution presented work, with a 15 dB conversion loss. This design performs well compared to reference mixers. With this report it will be shown that it is possible to make a simple and compact Doppler radar system in CMOS. / Denna avhandling bygger på en artikel av V. Issakov, presenterad 2009, där en lösning för att sammanslå en effektförstärkare med en mixer till en krets visades. Detta arbete tar denna lösning och förenklar det för användning vid en lägre frekvens. Målet är att implementera en dopplerradar i CMOS som kan detektera människor inom ett avstånd på 5 till 15 meter. Denna radar skulle kunna användas som ett inbrottslarm eller en automatisk strömbrytare. Rapporten kommer att presentera bakgrunden från Issakov’s arbete, grundläggande teori som används och genomförandet av det slutliga kretsschemat. Simuleringar visar att den presenterade lösningen fungerar, med en 15 dB konverteringsförlust. Denna konstruktion presterar väl jämfört med referens mixrar. Med denna rapport visas det att det är möjligt att göra ett enkelt och kompakt dopplerradarsystem i CMOS.

Continued scaling of CMOS devices with Si and SixGe1-x down to 22 nm design node or beyond will require the formation of ever shallower and more abrupt junctions with higher doping levels in order to manage the short channel effects. With the increasing importance of surface proximity and stress effects, the lateral diffusion in gate-extension overlap region strongly influences both threshold voltage roll-off degradation and DIBL increase by requiring an optimized abruptness and diffusion for better device performance. Therefore, the detailed understanding of defect-dopant interactions in the disordered and/or strained systems is essential to develop a predictive kinetic model for the evolution of dopant concentration and electrical activation profiles. Our density functional theory calculations provide the guidance for experimental designs to realize ultra-shallow junction formation required for future generations of nano-scale CMOS devices. Few systematic studies in epitaxially-grown SixGe1-x channel CMOS have been reported. The physical mechanisms of boron diffusion in strained SixGe1-x/Si heterojunction layers with different SixGe1-x layer thicknesses and Ge content (>50%) are addressed, especially with high temperature annealing. In addition, the effects of the fluorine incorporated during BF2 implant on boron diffusion are investigated to provide more insight into short channel device design. In this study, we investigate how short channel margins are affected by Ge mole fraction and SixGe1-x layer thickness in a compressively strained SixGe1-x/Si heterojunction PMOS with high temperature annealing. Series resistance characterization in S/D extension region and gate oxide interface trap characterization for Si, SixGe1-x, and Ge nMOSFETs are done. TCAD device simulation is also performed to evaluate which distributions of interface traps will significantly affect the electrical characteristics such as flatband voltage (VFB) shift and threshold voltage (Vth) shift based on capacitance-voltage (CV) and current-voltage (IV) curves. n+/p and p+/n diode structures are studied in order to decouple the electrical characteristics from the gated-diode (GD) MOSFETs. With the extraction of S/D series resistance from various channel lengths, possible reasons for performance degradation in SixGe1-x and Ge nMOSFETs, based on simulations, are proposed. / text

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This master thesis was part of a project at the Acreo Swedish ICT AB to investigate the 28 nm FDSOI CMOS process technology for the LTE front-end application. The project has resulted in a chip that contains different test circuits such as power amplifier (PA), mixer, low noise amplifier (LNA), RF power switch, and a receiver front-end. This thesis presents the evaluation of the RF power switch. At first, a stand-alone six-stacked single pole single throw (SPST) RF power switch was designed according to Rascher, and then it was modified to single pole double throw (SPDT) RF power switch according to the requirements of the project. This report presents an overview of the FDSOI CMOS process, basic theory of the RF switch, and the evaluation techniques. The post-simulation results showed that with the proper substrate biasing and matching (50 Ω), the RF switch will provide 2.5 dB insertion loss (IL) up to 27 dBm input power and over 30 dB isolation with 30 dBm input power at 2 GHz. / Detta examensarbete har varit en del av ett projekt på Acreo Swedish ICT AB för att undersöka 28 nm FDSOI CMOS teknik för LTE front-end tillämpningar. Projektet har resulterat i ett chip som innehåller olika testkretsar: effektförstärkare, mixer, RF-effektomkoppare, LNA, och en mottagarfront-end. Denna avhandling presenterar en utvärdering av RF-omkopplaren. En SPST RF-omkopplare med sex staplade transistor konstruerades enligt Rascher. Sedan modifierades konstruktionen till en SPDT-omkoppare i enlighet med kraven för projektet. Denna rapport presenterar en översikt över FDSOI CMOS-tekniken, grundläggande teori för en RF switch samt utvärderingsmetoder. Simuleringsresultaten visade att med rätt substratbiasering och matchning (50 Ω), så ger RF-omkopplaren 2,5 dB förlust (IL) på upp till 27 dBm ineffekt och över 30 dB isolering med 30 dBm ineffekt vid 2 GHz.