Quadrature digital modulation techniques are widely used in modern communication systems because of their high performance and flexibility. However, these advantages come at the cost of high power consumption. As a result, power consumption has to be taken into account as a main design factor of the modulator.<p>In this thesis, a low-power quadrature digital modulator in 0.18um CMOS is presented with the target system clock speed of 150 MHz. The quadrature digital modulator consists of several key blocks: quadrature direct digital synthesizer (QDDS), pulse shaping filter, interpolation filter and inverse sinc filter. The design strategy is to investigate different implementations for each block and compare the power consumption of these implementations. Based on the comparison results, the implementation that consumes the lowest power will be chosen for each block. First of all, a novel low-power QDDS is proposed in the thesis. Power consumption estimation shows that it can save up to 60% of the power consumption at 150 MHz system clock frequency compared with one conventional design. Power consumption estimation results also show that using two pulse shaping blocks to process I/Q data, cascaded integrator comb (CIC) interpolation structure, and inverse sinc filter with modified canonic signed digit (MCSD) multiplication consume less power than alternative design choices. These low-power blocks are integrated together to achieve a low-power modulator. The power consumption estimation after layout shows that it only consumes about 95 mW at 150 MHz system clock rate, which is much lower than similar commercial products. <p>The designed modulator can provide a low-power solution for various quadrature modulators. It also has an output bandwidth from 0 to 75 MHz, configurable pulse shaping filters and interpolation filters, and an internal sin(x)/x correction filter.

Due to continued transistor scaling, work function tuning of metal gates has become important for advanced CMOS applications. Specifically, this research has been undertaken to discover the tuning of the MoxSiyNz gate work function through the incorporation of nitrogen. Metal Oxide Semiconductor (MOS) capacitors were fabricated using thermal SiO2 as gate oxide on lightly doped p-type Si wafer. A molybdenum silicide (MoSi2) target was reactively sputtered at 10mTorr in presence of N2 and Ar. The gas flow ratio, RN = N2/ (N2+Ar), was adjusted to vary the nitrogen concentration in MoSiN films. The gate work function (Фm) was extracted from capacitance-voltage (CV) measurements using the VFB-tox method. Interfacial barrier heights were measured using internal photoemission (IPE) as an independent confirmation of the MoSiN gate work function. The work function was found to decrease linearly (from ~4.7eV to ~4.4eV) for increasing gas flow ratios (from 10% to 40%). Secondary ion mass spectrometry (SIMS) depth profiles suggested that the nitrogen concentration was relatively uniform throughout the film. X-Ray Photoelectron Spectroscopy (XPS) surface analysis showed a steady increase in the total nitrogen concentration (from ~20% to 32%) in these films as gas flow ratio was increased. These data suggests that the increase in nitrogen concentration in MoSiN films corresponds directly with the lowering of MoSiN work function. These results clearly demonstrate that the work function of MoxSiyNz can be varied ~0.3 eV by adjusting the nitrogen concentration. / October 2008

Many emerging applications call for wideband analog-to-digital converters and some require medium-to-high resolution. Incorporating such ADCs allows for shifting as much of the signal processing tasks as possible to the digital domain, where more flexible and programmable circuits are available. However, realizing such ADCs with the existing single stage architectures is very challenging. Therefore, parallel ADC architectures such as time-interleaved structures are used. Unfortunately, such architectures require high-speed high-precision sample-and-hold (S/H) stages that are challenging to implement. In this thesis, a parallel ADC architecture, namely, the frequency-translating hybrid ADC (FTH-ADC) is proposed to increase the conversion speed of the ADCs, which is also suitable for applications requiring medium-to-high resolution ADCs. This architecture addresses the sampling problem by sampling on narrowband baseband subchannels, i.e., sampling is accomplished after splitting the wideband input signals into narrower subbands and frequency-translating them into baseband where identical narrowband baseband S/Hs can be used. Therefore, lower-speed, lower-precision S/Hs are required and single-chip CMOS implementation of the entire ADC is possible. A proof of concept board-level implementation of the FTH-ADC is used to analyze the effects of major analog non-idealities and errors. Error measurement and compensation methods are presented. Using four 8-bit, 100 MHz subband ADCs, four 25 MHz Butterworth filters, two 64-tap FIR reconstruction filters, and four 10-tap FIR compensation filters, a total system with an effective sample rate of 200 MHz is implemented with an effective number of bits of at least 7 bits over the entire 100 MHz input bandwidth. In addition, one path of an 8-GHz, 4-bit, FTH-ADC system, including a highly-linear mixer and a 5th-order, 1 GHz, Butterworth Gm-C filter, is implemented in a 90 nm CMOS technology. Followed by a 4-bit, 4-GHz subband ADC, the blocks consume a total power of 52 mW from a 1.2 V supply, and occupy an area of 0.05 mm2. The mixer-filter has a THD ≤ 5% (26 dB) over its full 1 GHz bandwidth and provides a signal with a voltage swing of 350 mVpp for the subsequent ADC stage.

Estructures ressonants en forma de biga (p.e. ponts o palanques) són molt interessants com a element transductor en sensors físics, químics i biològics basats en sistemes micro-/nanoelectromecànics (M-/NEMS) degut a la seva simplicitat, al gran rang de dominis que poden sensar, i a la seva extremada alta sensibilitat. Aquesta tesis està focalitzada en el disseny, fabricació i caracterització de CMOS-MEMS monolítics basats en bigues ressonants a escala sub-micromètrica per a la seva utilització en la detecció ultra sensible de massa amb un dispositiu portable. Els ressonadors operen en mode dinàmic on la massa es mesurada com un canvi de la seva freqüència de ressonància que és induïda electrostàticament i llegida d'una forma capacitiva mitjançant un circuit CMOS integrat monolíticament. Dues aproximacions tecnològiques diferents són considerades per tal de fabricar bigues ressonants a escala sub-micromètrica sobre xips CMOS prèviament processats, possibilitant una integració monolítica: (i) post processant els xips CMOS amb tècniques de nano fabricació per obtenir les estructures ressonants o (ii) definint els ressonadors al mateix temps que els circuits CMOS. Per les dues aproximacions, es presenten dispositius de metall i de polysilici amb sensibilitats de massa sense precedents (per a sensors CMOS monolítics) dins el rang dels atto-/zeptograms. Es presenta una comparativa dels resultats aconseguits mitjançant les dues aproximacions tecnològiques.Es dissenyen circuits de lectura CMOS d'alta sensibilitat per amplificar el corrent capacitiu amb guanys de transimpedància (utilitzant una tecnologia comercial CMOS 0.35-&#956;m) de fins a 120 dB&#937; a 10 MHz possibilitant la detecció del desplaçament del ressonador amb resolucions de fins a ~10 fm/&#8730;Hz semblants a les obtingudes pels millors sistemes de detecció òptics reportats i sense la necessitat d'un equipament complexa. Es presenta la caracterització elèctrica, a l'aire i al buit, de dispositius CMOS-MEMS fabricats que corroboren la capacitat de l'aproximació monolítica presentada per mesurar la característica freqüencial de ressonadors a escala sub-micromètrica. S'aconsegueix una transducció electrostàtica òptima i es mesuren respostes freqüencials elèctriques amb pics elevats (fins a 20 dB o més) i grans canvis de fase (fins a 160º) al voltant de la freqüència de ressonància. També es reporten mesures on s'observen efectes de softening/harderning de la constant de molla i d'histèresis produïts per les no linealitats així com la detecció del moviment Brownià intrínsec demostrant el bon matching de soroll entre el ressonador i el circuit de lectura. També es presenten els resultats de calibració, de mesures en temps real, i d'anàlisi de la resolució dels dispositius fabricats obtenint valors de fins a ~30 zg/&#8730;Hz (equivalent a ~6 pg/cm2&#8730;Hz) en condicions de buit que indiquen la millora respecte a treballs anteriors en termes de sensibilitat, resolució i procés de fabricació.Es presenta i es testeja un circuit oscil·lador Pierce CMOS adaptat per a treballar amb ressonadors de ~10 MHz i amb resistències mecàniques equivalents de fins a 100 M&#937; demostrant que és factible la detecció d'attograms amb un dispositiu sensor completament portable. / Resonant beams structures are very attractive transducers for physical, chemical and biological sensors based on micro-/nanoelectromechanical systems (M-/NEMS) due to its simplicity, wide range of sensing domains, and extremely high sensitivity. This Ph.D. thesis is focused on the design, fabrication and characterization of monolithic CMOS-MEMS based on sub-micrometer scale resonant beams for its application in ultrasensitive mass detection with a portable device. The resonators operate in dynamic mode where the mass is measured as a change of its resonant frequency which is electrostatically induced and capacitive readout by means of a monolithically integrated CMOS circuitry. Two different technological approaches are considered to fabricate sub-micrometer scale resonant beams on pre-processed CMOS chips allowing a monolithic integration: (i) nano post-processing of the CMOS chip to obtain the resonant beams or (ii) definition of the resonant beams at the same time that the CMOS circuits. From both approaches, metal and polysilicon devices exhibiting unprecedented mass sensitivities (for monolithic CMOS sensors) in the atto-/zeptogram range are reported. Comparison of the results following both approaches is given.High-sensitivity readout CMOS circuits are specifically designed to amplify the capacitive current with transimpedance gains (using a commercial 0.35-&#956;m CMOS technology) up to 120 dB&#937; at 10 MHz allowing to detect the resonator displacement with resolutions up to ~10 fm/&#8730;Hz which are similar than the best reported optical readout systems without the need of a bulky setup.Electrical characterization, in air and in vacuum conditions, of fabricated CMOS-MEMS devices is presented corroborating the ability of the presented monolithic approach in measuring the frequency characteristics of sub-micrometer scale beam resonators. Optimal electrostatic transduction is achieved measuring electrical frequency responses with high peaks (up to 20 dB or more) and large phase shifts (up to 160º) around the resonance frequency. Measurements showing soft/hard-spring effect and hysteretic performance due to nonlinearities are also reported as well as the detection of intrinsic Brownian motion demonstrating the noise-matching between the resonator and the readout circuit. Results from calibration, real time mass measurements, and resolution analysis on fabricated devices obtaining values down to ~30 zg/&#8730;Hz (equivalent to ~6 pg/cm2&#8730;Hz) in vacuum conditions are also reported indicating the improvement from previous works in terms of sensitivity, resolution, and fabrication process.A specific CMOS Pierce oscillator circuit adapted to work with ~10 MHz beam resonators showing motional resistance up to 100 M&#937; is presented and tested demonstrating the feasible attogram detection with a completely portable sensor device.

L'échantillonneur-bloqueur est un dispositif central des systèmes de conversion analogique-numérique. Son utilisation dans des domaines d'applications sensibles comme le domaine biomédical place des exigences élevées sur la performance de l'échantillonneur. Les distorsions d'injection de charges, d'erreur d'échantillonnage et celle due aux variations de la constante de temps sont trois sources de non-linéarité qu'il est primordial d'évaluer pendant la conception. La modélisation analytique est l'une des méthodes employées afin d'estimer la distorsion du dispositif d'échantillonnage. Cependant, les méthodes analytiques courantes sont complexes ou ne tiennent pas compte des capacités parasites du commutateur analogique. La conception par la mise en oeuvre de procédures de caractérisation de la distorsion à l'aide de simulateurs analogiques de la famille SPICE donne une bonne estimation de la distorsion mais aboutit à des cycles de conception longs et fastidieux. Dans ce document, nous proposons deux méthodes d'évaluation de la distorsion de l'échantillonneur-bloqueur. Dans un premier temps, nous présenterons un nouveau modèle analytique simple de la distorsion. Notre modèle met en oeuvre l'approximation en série de Taylor afin de caractériser complètement les trois sources de distorsion de l'échantillonneur-bloqueur, incluant l'effet de substrat et les capacités parasites du commutateur analogique. Une autre contribution dans ce mémoire est de proposer un logiciel de simulation comportementale d'aide à la conception des échantillonneurs-bloqueurs dans le procédé MOS submicronique 0.18 µm. Ce logiciel permet de réduire le cycle de conception et d'évaluer efficacement la distorsion de l'échantillonneur-bloqueur. Afin d'atteindre cet objectif, nous avons intégré le modèle BSIM3 du transistor au logiciel que nous avons développé en langage Java. Nous verrons avec des exemples d'application comment les paramètres de chacune des sources de distorsion agissent sur la gamme dynamique de l'échantillonneur-bloqueur par les méthodes que nous proposons. ______________________________________________________________________________ MOTS-CLÉS DE L’AUTEUR : Échantillonneur-blogueur, Distorsion, CMOS, Modélisation comportementale.

Les dimensions dels transistors disminueixen per a cada nova tecnologia CMOS. Aquest alt nivell d'integració complica el procés de fabricació dels circuits integrats, apareixent nous mecanismes de fallada. En aquest sentit, els mètodes de diagnosi actuals no són capaços d'assumir els nous reptes que sorgeixen per a les tecnologies nanomètriques. A més, la inspecció física de fallades (Failure Analysis) no es pot aplicar des d'un bon començament, ja que els costos de la seva utilització són massa alts. Per aquesta raó, conèixer el comportament dels defectes i dels seus mecanismes de fallada és imprescindible per al desenvolupament de noves metodologies de diagnosi que puguin superar aquests nous reptes. En aquest context, aquesta tesi presenta l'anàlisi dels mecanismes de fallada i proposa noves metodologies de diagnosi per millorar la localització de ponts (bridge) i oberts (open). Per a la diagnosi de ponts, alguns treballs s'han beneficiat de la informació obtinguda durant el test de corrent (IDDQ). No obstant no han tingut en compte l'impacte del corrent de dowsntream. Per aquesta raó, en aquesta tesi s'analitza l'impacte d'aquest corrent degut als ponts i la seva dependència amb la tensió d'alimentació (VDD). A més, es presenta una nova metodologia de diagnosi basada en els múltiples nivells de corrent. Aquesta tècnica considera els corrents generats per les diferents xarxes connectades pel pont. Aquesta metodologia s'ha aplicat amb èxit a un conjunt de xips defectuosos de tecnologies de 0.18 µm i 90 nm.Com alternativa a les tècniques basades en corrent, els shmoo plots també poden ser útils per a la diagnosi. Tradicionalment s'ha considerat que valors baixos de VDD són més apropiats per a la detecció de ponts. Tanmateix es demostra en aquesta tesi que en presència de ponts connectant xarxes equilibrades, valors alts de VDD són fins i tot més apropiats que tensions baixes, amb la conseqüent implicació que això té per a la diagnosi.En relació als oberts, s'ha dissenyat i fabricat un xip amb la inclusió intencionada d'oberts complets (full opens) i oberts resistius. Experiments fets amb els xips demostren l'impacte de les capacitats d'acoblament de les línies veïnes. A més, pels oberts resistius s'ha comprovat la influència de l'efecte història i de la localització de l'obert en el retard. Tradicionalment s'ha considerat que el retard màxim s'obté quan un obert resistiu es troba al principi de la línia. No obstant això no es pot generalitzar a oberts poc resistius, ja que en aquests casos es demostra que el màxim retard s'obté per a una localització intermèdia. A partir dels resultats experimentals obtinguts amb el xip, s'ha desenvolupat una nova metodologia per a la diagnosi d'oberts complets a les línies d'interconnexió. Aquest mètode divideix la línia en diferents segments segons la informació de layout de la pròpia línia. Aleshores coneixent els valors de les línies veïnes, es prediu la tensió del node flotant, la qual es compara amb el resultat experimental obtingut a la màquina de test. Aquest mètode s'ha aplicat amb èxit a un seguit de xips defectuosos pertanyents a una tecnologia de 0.18 µm.Finalment, s'ha analitzat l'impacte que tenen els corrents de túnel a través del terminal de porta en presència d'un obert complet. Com les dimensions disminueixen per a cada nova tecnologia, l'òxid de porta és suficientment prim com per generar corrents de túnel que influencien el node flotant. Aquests corrents generen una evolució temporal al node flotant fins fer-lo arribar a un estat quiescent, el qual depèn de la tecnologia. Es comprova que aquestes evolucions temporals són de l'ordre de segons per a una tecnologia de 0.18 µm. Tanmateix les simulacions demostren que aquests temps disminueixen fins a uns quants µs per a tecnologies futures. Degut a l'impacte dels corrents de túnel, un seguit d'oberts complets s'han diagnosticat en xips de 0.18 µm. / Transistor dimensions are scaled down for every new CMOS technology. Such high level of integration has increased the complexity of the Integrated Circuits (ICs) manufacturing process, arising new complex failure mechanisms. However, present diagnosis methodologies cannot afford the challenges arisen for future technologies. Furthermore, physical failure analysis, although indispensable, is not feasible on its own, since it requires high cost equipment, tools and qualified personnel. For this reason, a detailed understanding and knowledge of defect behaviours is a key factor for the development of improved diagnosed methodologies to overcome the challenges of nanometer technologies. In this context, this thesis presents the analysis of existing and new failure mechanisms and proposed new diagnosis methodologies to improve the diagnosis of faults, focused on bridging and open faults.IDDQ is a well known technique for the diagnosis of bridging faults. However, previous works have not considered the impact of the downstream current for the diagnosis of such faults. In this thesis, the impact and the dependence of the downstream current with the power supply voltage (VDD) is analyzed and experimentally measured. Furthermore, a multiple level IDDQ based diagnosis technique is presented. This method takes benefit from the currents generated by the different network excitations. This technique is successfully applied to real defective devices from 0.18 µm and 90 nm technologies.As an alternative to current based techniques, shmoo plots can be also useful for diagnosis purposes. Low voltage has been traditionally considered as an advantageous condition for the detection of bridging faults. However, it is demonstrated that in presence of bridges connecting balanced n- and p-networks, high VDD values are also advantageous for the detection of bridges, which has its direct translation into diagnosis application. Experimental evidence of this fact is presented.Related to open faults, an experimental chip has been designed and fabricated in a 0.35 µm technology, where full and resistive open defects have been intentionally added. Different experiments have been carried out so that the impact of the neighbouring coupling capacitances has been quantified. Furthermore, for resistive opens, experiments have demonstrated the influence of the history effect and the location of the defect on the delay. Traditionally, it has been reported that the highest delay is obtained when the resistive open is located at the beginning of the net. Nevertheless, this thesis demonstrates that this is not true for low resistive open, since the highest delay is obtained for an intermediate location. Experimental measurements prove this behaviour.Derived from the results obtained with the fabricated chip, a new methodology for the diagnosis of interconnect full open defects is developed. The FOS (Full Open Segment) method divides the interconnect line into different segments based on the topology of the faulty line. Knowing the logic state of the neighbouring lines, the floating net voltage is predicted and compared with the experimental results obtained on the tester. This method has been successfully applied to a set of 0.18 µm defective devices. Finally, the impact of the gate tunnelling leakage currents on the behaviour of full open defects has also been analyzed. As technology dimensions are scaled down, the oxide thickness is thin enough so that the gate tunnelling leakage currents influence the behaviour of floating lines. They cause transient evolutions on the floating node until reaching the steady state, which is technology dependent. It is experimentally demonstrated that these evolutions are in the order of seconds for a 0.18µm technology. However, for future technologies, simulations show that the evolutions decrease down to a few µs. Based on this factor, some full open faults present in 0.18 µm technology devices are diagnosed.

Today, the mobile communication systems can be found everywhere due to thelow cost and high degree integration level which is achievable with CMOS. Theuser can use a number of applications using only one device. The transmitteris one of the main blocks in communication systems for transmitting the signal,where the RF power a mplifier (PA) amplifies the RF signal to the r equiredoutput power so that signal can reach the r eceiver. Nowadays mostly transmitteremploys such modulation schemes which have high data rate and to amplify suchsignals, a linear PA is required. The efficiency of the PA should also be high, sothat it can provide high output power to load without consuming much poweritself.This thesis work describes the “CMOS Power Amplifier for IEEE 802.11g/nstandard (2.4GHz) in 65nm process”. The PA is a two stage amplifier biasedin Class AB mode with LC type input matching. The inter-stage matching iscarried out by the RF choke of the driver stage and the input capacitance of thepower stage. The output of the PA is power matched to the load. A linearizingtechnique is implemented to make PA more linear. The simulation results showsthat the designed PA gives 1dB compression point of +23.36dBm, a gain of26.82dB, a power added efficiency of 30%, a linear current of 122.30mA providing18dBm power to load and saturated output power of 24.45dBm.

Reconfigurable impedance matching networks are an integral part of multiband radio-frequency (RF) transceivers. They are used to compensate for the input/output impedance variations between the different blocks caused by switching the frequency band of operation or by adjusting the output power level. Various tuning techniques have been developed to construct tunable impedance matching networks employing solid-state p-i-n diodes and varactors. At millimeter-wave frequencies, the increased loss due to the low quality factor of the solid-state devices becomes an important issue. Another drawback of the solid-state tuning elements is the increased nonlinearity and noise at higher RF power levels. The objective of the research described in this thesis is to investigate the feasibility of using RF microelectromechanical systems (RF-MEMS) technology to develop reconfigurable impedance matching networks. Different types of tunable impedance matching networks with improved impedance tuning range, power handling capability, and lower insertion loss have been developed. Another objective is to investigate the realization of a fully integrated one-chip solution by integrating MEMS devices in standard processes used for RF integrated circuits (RFICs). A new CMOS-MEMS post-processing technique has been developed that allows the integration of tunable RF MEMS devices with vertical actuation within a CMOS chip. Various types of CMOS-MEMS components used as tuning elements in reconfigurable RF transceivers have been developed. These include tunable parallel-plate capacitors that outperform the available CMOS solid-state varactors in terms of quality factor and linearity. A tunable microwave band-pass filter has been demonstrated by employing the proposed RF MEMS tunable capacitors. For the first time, CMOS-MEMS capacitive type switches for microwave and millimeter-wave applications have been developed using TSMC 0.35-µm CMOS process employing the proposed CMOS-MEMS integration technique. The switch demonstrates an excellent RF performance from 10-20 GHz. Novel MEMS-based reconfigurable impedance matching networks integrated in standard CMOS technologies are also presented. An 8-bit reconfigurable impedance matching network based on the distributed MEMS transmission line (DMTL) concept operating at 13-24 GHz is presented. The network is implemented using standard 0.35-µm CMOS technology and employs a novel suspended slow-wave structure on a silicon substrate. To our knowledge, this is the first implementation of a DMTL tunable MEMS impedance matching network using a standard CMOS technology. A reconfigurable amplifier chip for WLAN applications operating at 5.2 GHz is also designed and implemented. The amplifier achieves maximum power gain under variable load and source impedance conditions by using the integrated RF-MEMS impedance matching networks. This is the first single-chip implementation of a reconfigurable amplifier using high-Q MEMS impedance matching networks. The monolithic CMOS implementation of the proposed RF MEMS impedance matching networks enables the development of future low-cost single-chip RF multiband transceivers with improved performance and functionality.

Quadrature digital modulation techniques are widely used in modern communication systems because of their high performance and flexibility. However, these advantages come at the cost of high power consumption. As a result, power consumption has to be taken into account as a main design factor of the modulator.<p>In this thesis, a low-power quadrature digital modulator in 0.18um CMOS is presented with the target system clock speed of 150 MHz. The quadrature digital modulator consists of several key blocks: quadrature direct digital synthesizer (QDDS), pulse shaping filter, interpolation filter and inverse sinc filter. The design strategy is to investigate different implementations for each block and compare the power consumption of these implementations. Based on the comparison results, the implementation that consumes the lowest power will be chosen for each block. First of all, a novel low-power QDDS is proposed in the thesis. Power consumption estimation shows that it can save up to 60% of the power consumption at 150 MHz system clock frequency compared with one conventional design. Power consumption estimation results also show that using two pulse shaping blocks to process I/Q data, cascaded integrator comb (CIC) interpolation structure, and inverse sinc filter with modified canonic signed digit (MCSD) multiplication consume less power than alternative design choices. These low-power blocks are integrated together to achieve a low-power modulator. The power consumption estimation after layout shows that it only consumes about 95 mW at 150 MHz system clock rate, which is much lower than similar commercial products. <p>The designed modulator can provide a low-power solution for various quadrature modulators. It also has an output bandwidth from 0 to 75 MHz, configurable pulse shaping filters and interpolation filters, and an internal sin(x)/x correction filter.

Many researchers and engineers designing laser drivers for data rates at or above 10 gigabits per second (Gbps) implemented their designs using integrated circuit technologies that provide high bandwidth and good quality passive components such as GaAs, silicon bipolar, and InP. However, in low-cost and high volume short-haul applications at data rates of around 10 Gbps (such as LAN, MAN, and board-to-board interconnection), there has been an increasing interest in commercial CMOS technology for implementing the laser driver. This is because CMOS technology has unique advantages such as low power and low cost of fabrication that are the result of high yield and a high degree of integration. Therefore, the objective of this research in this dissertation is to investigate the possibility of implementing a high-speed CMOS laser driver for these cost sensitive applications. The high-speed CMOS laser drivers designed in this research are of two types. The first type is a low power laser driver for driving a vertical cavity surface emitting laser (VCSEL). The other driver type is a high current laser driver for driving edge-emitting lasers such as double-heterojunction (DH), multiquantum well (MQW), or Febry-Perrot (FP) lasers. The parasitic effects of the layout geometry are crucial in the design of the high-speed laser drivers. Thus, in this research, all simulations contain a complete set of parasitic elements extracted from the layout of the laser driver. To test laser drivers, chip-on-board (COB) technology is employed, and printed circuit boards (PCBs) to test the laser drivers are designed at the same time as the laser drivers themselves and manufactured specifically for these tests. This research makes two significant new contributions to the technology that are reported and described here. One is the first 10 Gbps performance of a differential CMOS laser driver with better than 10-14 bit-error-rate (BER). The second is the first demonstration of a heterogeneous integration method to integrate independently grown and customized thin film lasers onto CMOS laser driver circuits to form an optical transmitter.