Fluorescence lifetime sensing using time correlated single photon counting (TCSPC) is a key analytical tool for molecular and cell biology research, medical diagnosis and pharmacological development. However, commercially available TCSPC equipment is bulky, expensive and power hungry, typically requiring iterative software post-processing to calculate the fluorescence lifetime. Furthermore, the technique is restrictively slow due to a low photon throughput limit which is necessary to avoid distortions caused by TCSPC pile-up. An investigation into CMOS compatible multimodule architectures to miniaturise the standard TCSPC set up, allow an increase in photon throughput by overcoming the TCSPC pile-up limit, and provide fluorescence lifetime calculations in real-time is presented. The investigation verifies the operation of the architectures and leads to the selection of optimal parameters for the number of detectors and timing channels required to overcome the TCSPC pile-up limit by at least an order of magnitude. The parameters are used to implement a low power miniaturised sensor in a 130 nm CMOS process, combining single photon detection, multiple channel timing and embedded pre-processing of the fluorescence lifetime, all within a silicon area of < 2 mm2. Single photon detection is achieved using an array of single photon avalanche diodes (SPADs) arranged in a digital silicon photomultiplier (SiPM) architecture with a 10 % fill-factor and a compressed 250 ps output pulse, which provides a photon throughput of > 700 MHz. An array of time-interleaved time-to-digital converters (TI-TDCs) with 50 ps resolution and no processing dead-time records up to eight photon events during each excitation period, significantly reducing the effect of TCSPC pile-up. The TCSPC data is then processed using an embedded centre-of-mass method (CMM) pre-calculation to produce single exponential fluorescence lifetime estimations in real-time. The combination of high photon throughput and real-time calculation enables advances in applications such as fluorescence lifetime imaging microscopy (FLIM) and time domain fluorescence lifetime activated cell sorting. To demonstrate this, the device is validated in practical bulk sample fluorescence lifetime, FLIM and simulated flow based experiments. Photon throughputs in excess of the excitation frequency are demonstrated for a range of organic and inorganic fluorophores for minimal error in lifetime calculation by CMM (< 5 %).

En el presente trabajo de tesis se realizó el diseño de un circuito de protección contra ataques del tipo Differential Power Analysis (DPA) aplicado a tarjetas inteligentes. Este tipo de tarjetas presenta la misma apariencia física de una tarjeta de crédito pero en su estructura cuenta con un circuito integrado. Se utilizó la tecnología AMS 0.35m de la compañía Austriamicrosystem, y se aplicó la técnica denominada Atenuación de Corriente. Esta se basa en la implementación de un circuito ubicado entre la fuente de alimentación y el procesador criptográfico de la tarjeta inteligente, el cual logra disminuir las variaciones de consumo de corriente presentes durante una operación criptográfica. El circuito de protección se dividió en tres bloques: Sensor de Corriente, Amplificador de Transimpedancia e Inyector de Corriente. Cada uno de estos bloques fue diseñado tomando criterios del diseño de circuitos integrados analógicos, tales como consumo de potencia, área ocupada y ganancia. Para esta etapa de diseño se utilizó el modelo Level 1 del transistor MOSFET. Posteriormente, se realizaron simulaciones a cada uno de los bloques del circuito de protección usando el software Cadence. Finalmente, una vez alcanzados los requerimientos establecidos, se procedió al desarrollo del layout físico del circuito diseñado. El circuito diseñado logra una atenuación de las variaciones de consumo de corriente del 86%. Entre sus principales características se puede mencionar que consume 35.5mW , ocupa 2 60000m y presenta 96MHz de ancho de banda. / Tesis

The adaptation of standard integrated circuit (IC) technology for biosensors in drug discovery pharmacology, neural interface systems, environmental sensors and electrophysiology requires electrodes to be electrochemically stable, biocompatible and affordable. Unfortunately, the ubiquitous IC technology, complementary metal oxide semiconductor (CMOS), does not meet the first of these requirements. For devices intended only for research, modification of CMOS by post-processing using cleanroom facilities has been achieved by others. However, to enable adoption of CMOS as a basis for commercial biosensors, the economies of scale of CMOS fabrication must be maintained by using only low-cost post-processing techniques. The scope of this work was to develop post-processing methods that meet the electrochemical and biocompatibility requirements but within the low-cost constraint. Several approaches were appraised with the two most promising designs taken forward for further investigation. Firstly, a process was developed whereby the corrodible aluminium is anodised to form nanoporous alumina and further processed to optimise its impedance. A second design included a noble metal in the alumina pores to enhance further the electrical characteristics of the electrode. Experiments demonstrated for the first time the ability to anodise CMOS metallisation to form the desired electrodes. Tests showed the electrode addressed the problems of corrosion and presented a surface that was biocompatible with the NG108-15 neuronal cell line. Difficulties in assessing the influence of alumina porosity led to the development of a novel cell adhesion assay that showed for the first time neuronal cells adhere preferentially to large pores rather than small pores or planar aluminium. It was also demonstrated that porosity can be manipulated at room temperature by modifying the anodising electrolyte with polyethylene glycol. CMOS ICs were designed as multiple electrode arrays and optimised for neuronal recordings. This utilised the design incorporating a noble metal deposited into the porous alumina. Deposition of platinum was only partially successful, with better results using gold. This provided an electrode surface suitable for electric cell-substrate impedance sensors (ECIS) and many other sensor applications. Further processing deposited platinum black to improve signal-to-noise ratio for neuronal recordings. The developed processes require no specialised semiconductor fabrication equipment and can process CMOS ICs on laboratory or factory bench tops in less than one hour. During the course of electrode development, new methods for biosensor packaging were assessed: firstly, a biocompatible polyethylene glycol mould process was developed for improved prototype assembly. Secondly, a commercial ‘partial encapsulation’ process (Quik-Pak, U.S.) was assessed for biocompatibility. Cell vitality tests showed both methods were biocompatible and therefore suitable for use in cell-based biosensors. The post-processed CMOS electrode arrays were demonstrated by successfully recording neuronal cell electrical activity (action potentials) and by ECIS with a human epithelial cell line (Caco2). It is evident that these developments may provide a missing link that can enable commercialisation of CMOS biosensors. Further work is being planned to demonstrate the technology in context for specific markets.

The ability to resolve multiple fluorescent emissions from different biological targets in video rate applications, such as endoscopy and intraoperative imaging, has traditionally been limited by the use of filter-based imaging systems. Hyper and multispectral imaging facilitate the detection of both spatial and spectral information in a single data acquisition, however, instrumentation for spatiospectral data acquisition is typically complex, bulky and expensive. This thesis seeks to overcome these limitations by using recently commercialised compact and robust hyper/multispectral cameras based on spectrally resolved detector arrays. Following sensor calibrations, which devoted particular attention to the angular sensitivity of the sensors, we integrated spectrally resolved detector arrays into a wide-field and an endoscopic imaging platform. This allowed multiplexed reflectance and fluorescence imaging with spectrally resolved detector array technology in vitro, in tissue mimicking phantoms, in an ex vivo oesophageal model and in vivo in a mouse model. A hyperspectral linescan sensor was first integrated in a wide-field near-infrared reflectance based imaging set-up to assess the suitability of spectrally resolved detector arrays for in vivo imaging of exogenous fluorescent contrast agents. Using this fluorescence hyperspectral imaging system, we could accurately resolve the presence and concentration of seven fluorescent dyes in solution. We also demonstrated high spectral unmixing precision, signal linearity with dye concentration, at depth in tissue mimicking phantoms, and delineation of four fluorescent dyes in vivo. After the successful demonstration of multiplexed fluorescence imaging in a wide-field set-up, we proceeded to combine near-infrared multiplexed fluorescence imaging with visible light spectral reflectance imaging in an endoscopic set-up. A multispectral endoscopic imaging system, capable of simultaneous reflectance and fluorescence imaging, was developed around two snapshot spectrally resolved detector arrays. In the process of system integration and characterisation, methods to characterise and predict the imaging performance of spectral endoscopes were developed. With the endoscope we demonstrated simultaneous imaging and spectral unmixing of chemically oxy/deoxygenated blood and three fluorescent dyes in a tissue mimicking phantom, and of two fluorescent dyes in an ex vivo oesophageal porcine model. With further developments, this technology has the potential to become applicable in medical imaging for detection of diseases such as gastrointestinal cancers.

Made available in DSpace on 2014-06-12T17:41:04Z (GMT). No. of bitstreams: 2 arquivo7526_1.pdf: 7264753 bytes, checksum: 764085c312809041966e34bffa171d8d (MD5) license.txt: 1748 bytes, checksum: 8a4605be74aa9ea9d79846c1fba20a33 (MD5) Previous issue date: 2010 / Esta dissertação descreve o projeto de dois amplificadores de baixo ruído (LNA), que é um dos blocos mais relevantes do sistema de recepção de rádio frequencia. Os circuitos, desenvolvidos em tecnologia CMOS 0,35 m da (Austria Micro System), foram baseados na norma IEEE 802.15.4 para serem aplicados a sistemas de redes de sensores sem fio. Apresenta-se uma dedução detalhada do fator de ruído para a configuração de fonte comum com degeneração indutiva, incluindo o ruído induzido no gate e o ruído devido a resistência parasita do gate, bem como duas adaptações de uma técnica de otimização para a figura de ruído em função do tamanho do transistor e da indutância de gate. Por fim, são apresentados dois casos de testes para operar em 915 MHz com seus desempenhos vericados através de simulações

Estágio realizado no CERN e orientado pelo Doutor Paulo Rodrigues Simões Moreira / Tese de mestrado integrado. Engenharia Electrotécnica e de Computadores (Major Telecomunicações). Faculdade de Engenharia. Universidade do Porto. 2009

Tese de mestrado integrado. Engenharia Electrotécnica e de Computadores (Major telecomunicações). Faculdade de Engenharia. Universidade do Porto. 2009

<p>Today’s microprocessors with millions of transistors perform high-complexity computing at multi-gigahertz clock frequencies. The ever-increasing chip size and speed call for new methodologies in clock distribution network. Conventional global synchronization techniques exhibit many drawbacks in the advanced VLSI chips such as high-speed microprocessors. A significant percentage of the total power consumption in a microprocessor is dissipated in the clock distribution network. Also since the chip dimensions increase, clock skew management becomes very challenging in the framework of conventional methodology. Long interconnect delays limit the maximum clock frequency and become a bottleneck for future microprocessor design. In such a situation, new alternative techniques for synchronization in system-on-chip are demanded.</p><p>This thesis presents new alternatives for traditional clocking and synchronization methods, in which, speed and power consumption bottlenecks are treated. For this purpose, two new techniques based on mesochronous synchronization and resonant clocking are investigated. The mesochronous synchronization technique deals with remedies for skew and delay management. Using this technique, clock frequency up to 5 GHz for on-chip communication is achievable in 0.18-<em>μ</em>m CMOS process. On the other hand the resonant clocking solves significant power dissipation problem in the clock network. This method shows a great potential in power saving in very large-scale integrated circuits. According to measurements, 2.3X power saving in clock distribution network is achieved in 130-nm CMOS process. In the resonant clocking, oscillator plays a crucial role as a clock generator. Therefore an investigation about oscillators and possible techniques for jitter and phase noise reduction in clock generators has been done in this research framework. For this purpose a study of injection locking phenomenon in ring oscillators is presented. This phenomenon can be used as a jitter suppression mechanism in the oscillators. Also a new implementation of the DLL-based clock generators using ring oscillators is presented in 130-nm CMOS process. The measurements show that this structure operates in the frequency range of 100 MHz-1.5 GHz, and consumes less power and area compared to the previously reported structures. Finally a new implementation of a 1.8-GHz quadrature oscillator with wide tuning range is presented. The quadrature oscillators potentially can be used as future clock generators where multi-phase clock is needed.</p> / Report code: LiU-TEK-LIC-2006:22

As CMOS processes size continues to shrink, a number of factors limit the ability of analog circuit performance to scale with the process. These issues include smaller transistor intrinsic gains and lower supply voltages. However, scaling continues to increase the speed and decrease the power of digital circuits. In this thesis, an active time-based integrator is proposed to replace amplifiers. The integrator, implemented using highly digital ring oscillators, seeks to take advantage of benefits offered by technology scaling while negating the issues of low gain and low supply voltages. The proposed integrator topology is used in a 20MHz 4th order continuous-time analog filter. Designed in a 90nm CMOS process, the time-based continuous-time filter achieves superior noise and linearity performance compared to state-of-the-art conventional active RC filters in simulations. / Graduation date: 2012 / Access restricted to the OSU Community at author's request from June 17, 2011 - June 17, 2012

The development of the transistor and its continuous down-scaling has allowed during the last decades the appearance of cheap wireless communication systems targeting consumer products. The complexity of these systems has increased dramatically during the last years, mainly fueled by both the Moore law and improvements in communication theory. Originally, the radio transceivers were composed of only a few transistors, and supported simple analog modulation schemes. Currently, radio transceivers are composed of thousands of transistors including not only radio/analog blocks but also a huge amount of digital circuitry as well. These radios use advanced digital modulation schemes, channel coding, and multiple access schemes. Despite the fact that digital circuits currently offer an impressive performance, pure digital signal processing of radio signals remains limited for relatively low frequencies below a few hundred MHz. On the other hand, frequency bands used in current mobile applications span from around 800MHz up to 6 GHz and hence demand the use of analog circuits to down-convert the radio signals to lower frequencies that are suitable for digital processing. The group of circuits that form this part of the receiver is known as the radio receiver front-end. The design of modern radio receiver front-ends has many challenges. One requirement is support of a multitude of standards with bands that are scattered all along the mobile radio spectrum. Accordingly, the noise and linearity specifications for these front-ends are very stringent. Also, these specifications have to be accomplished using low-power, low-cost, highly integrated circuit solutions. This thesis presents the design of multi-band multi-standard receiver front-ends for fourth generation mobile communications. A novel methodology that speeds up the development of multi-band multi-standard RF blocks by automating some steps in the design is shown. Examples of submicron and nanometer CMOS wideband receiver front-ends targeting 4G mobile applications are presented. New techniques for inductorless wideband front-ends using current-mode technology are presented. Finally, novel RF calibration techniques to cope with process, voltage, and temperature variations in modern CMOS processes are demonstrated. / QC 20100806 / RaMSiS