The technology evolution and complexity of new circuit applications involve emerging reliability problems and even more sensitivity of integrated circuits (ICs) to electrostatic discharge (ESD)-induced damage. Regardless of the aggressive evolution in downscaling and subsequent improvement in applications' performance, ICs still should comply with minimum standards of ESD robustness in order to be commercially viable. Although the topic of ESD has received attention industry-wide, the design of robust protection structures and circuits remains challenging because ESD failure mechanisms continue to become more acute and design windows less flexible. The sensitivity of smaller devices, along with a limited understanding of the ESD phenomena and the resulting empirical approach to solving the problem have yielded time consuming, costly and unpredictable design procedures. As turnaround design cycles in new technologies continue to decrease, the traditional trial-and-error design strategy is no longer acceptable, and better analysis capabilities and a systematic design approach are essential to accomplish the increasingly difficult task of adequate ESD protection-circuit design. This dissertation presents a comprehensive design methodology for implementing custom on-chip ESD protection structures in different commercial technologies. First, the ESD topic in the semiconductor industry is revised, as well as ESD standards and commonly used schemes to provide ESD protection in ICs. The general ESD protection approaches are illustrated and discussed using different types of protection components and the concept of the ESD design window. The problem of implementing and assessing ESD protection structures is addressed next, starting from the general discussion of two design methods. The first ESD design method follows an experimental approach, in which design requirements are obtained via fabrication, testing and failure analysis. The second method consists of the technology computer aided design (TCAD)-assisted ESD protection design. This method incorporates numerical simulations in different stages of the ESD design process, and thus results in a more predictable and systematic ESD development strategy. Physical models considered in the device simulation are discussed and subsequently utilized in different ESD designs along this study. The implementation of new custom ESD protection devices and a further integration strategy based on the concept of the high-holding, low-voltage-trigger, silicon controlled rectifier (SCR) (HH-LVTSCR) is demonstrated for implementing ESD solutions in commercial low-voltage digital and mixed-signal applications developed using complementary metal oxide semiconductor (CMOS) and bipolar CMOS (BiCMOS) technologies. This ESD protection concept proposed in this study is also successfully incorporated for implementing a tailored ESD protection solution for an emerging CMOS-based embedded MicroElectroMechanical (MEMS) sensor system-on-a-chip (SoC) technology. Circuit applications that are required to operate at relatively large input/output (I/O) voltage, above/below the VDD/VSS core circuit power supply, introduce further complications in the development and integration of ESD protection solutions. In these applications, the I/O operating voltage can extend over one order of magnitude larger than the safe operating voltage established in advanced technologies, while the IC is also required to comply with stringent ESD robustness requirements. A practical TCAD methodology based on a process- and device- simulation is demonstrated for assessment of the device physics, and subsequent design and implementation of custom P1N1-P2N2 and coupled P1N1-P2N2//N2P3-N3P1 silicon controlled rectifier (SCR)-type devices for ESD protection in different circuit applications, including those applications operating at I/O voltage considerably above/below the VDD/VSS. Results from the TCAD simulations are compared with measurements and used for developing technology- and circuit-adapted protection structures, capable of blocking large voltages and providing versatile dual-polarity symmetric/asymmetric S-type current-voltage characteristics for high ESD protection. The design guidelines introduced in this dissertation are used to optimize and extend the ESD protection capability in existing CMOS/BiCMOS technologies, by implementing smaller and more robust single- or dual-polarity ESD protection structures within the flexibility provided in the specific fabrication process. The ESD design methodologies and characteristics of the developed protection devices are demonstrated via ESD measurements obtained from fabricated stand-alone devices and on-chip ESD protections. The superior ESD protection performance of the devices developed in this study is also successfully verified in IC applications where the standard ESD protection approaches are not suitable to meet the stringent area constraint and performance requirement.

Low noise low division 2 GHz RF synthesizer integrated circuits (ICs) are conventionally implemented in some form of HBT process such as SiGe or GaAs. The research in this dissertation differs from convention, with the aim of implementing a synthesizer IC in a more convenient, low-cost Si-based CMOS process. A collection of techniques to push towards the noise and frequency limits of CMOS processes, and possibly other IC processes, is then one of the research outcomes. In a synthesizer low N-divider ratios are important, as high division ratios would amplify in-band phase noise. The design methods deployed as part of this research achieve low division ratios (4 ≤ N ≤ 33) and a high phase comparison frequency (>100 MHz). The synthesizer IC employs a first-order fractional-N topology to achieve increased frequency tuning resolution. The primary N-divider was implemented utilising current mode logic (CML) and the fractional accumulator utilising conventional CMOS. Both a conventional CMOS phase frequency detector (PFD) and a CML PFD were implemented for benchmarking purposes. A custom-built 4.4 GHz synthesizer circuit employing the IC was used to validate the research. In the 4.4 GHz synthesizer circuit, the prototype IC achieved a measured in-band phase noise plateau of L( f ) = -113 dBc/Hz at a 100 kHz frequency offset, which equates to a figure of merit (FOM) of -225 dBc/Hz. The FOM compares well with existing, but expensive, SiGe and GaAs HBT processes. Total IC power dissipation was 710 mW, which is considerably less than commercially available GaAs designs. The complete synthesizer IC was implemented in Austriamicrosystems‟ (AMS) 0.35 μm CMOS process and occupies an area of 3.15 x 2.18 mm2. / Dissertation (MEng)--University of Pretoria, 2010. / Electrical, Electronic and Computer Engineering / unrestricted

Die mikromechanische Gleichspannungswandlung basierend auf verschiebungsabhängigen Kapazitäten stellt eine Alternative zu etablierten rein elektronischen Wandlern für den Spezialfall der kapazitiven oder piezoelektrischen Verbraucher dar. Durch ihre kleine Bauform und den Verzicht auf Induktivitäten bietet sie den Vorteil der On-Chip-MEMS- und CMOS-Integration und ermöglicht die Bereitstellung hoher elektrischer Gleichspannungen aus den verfügbaren Grundspannungen der Elektronik (z. B. 3, 5 bzw. 12 V). Von hohen Polarisationsspannungen profitieren nicht nur kapazitive Sensoren und Aktoren, sondern auch piezoelektrische Messverfahren. Diese Arbeit stellt eine umfangreiche Übersicht und Bewertung der möglichen Bauformen mikromechanischer Gleichspannungswandler sowie die konkrete Umsetzung, Charakterisierung und Modellbildung eines resonant arbeitenden Wandlers vor. Es wird auf Besonderheiten und Probleme im Entwurf eingegangen und ausgehend von den Ergebnissen ein Konzeptentwurf für einen optimierten resonanten Gleichspannungswandler erarbeitet.:1 Einleitung 2 Theoretische Grundlagen 3 Ausführungsvarianten von MEMS-DC/DC-Wandlern 4 Designstudie und Umsetzung des resonanten Funktionsprinzips 5 Zusammenfassung und Ausblick / Micromechanical DC/DC conversion based on variable capacitances is an alternative to established electronic voltage converters, which does not require bulky inductors and is suitable for capacitive and piezoelectric loads. The converters are capable of boosting up the polarization voltage from CMOS and electronic levels (3, 5, 12 V), which is beneficial not only for capacitive sensors and actuators but also for piezoelectric sensing. Advantages of this method are the on-chip- and CMOS-integrability. This thesis introduces a comprehensive overview and evaluation of possible designs as well as the practical application, characterization and modeling of a resonant micromechanical DC/DC converter. Innovative claims include a test board for the characterization of resonant DC/DC converters and a SPICE behavioral model of the device, considering parasitic effects. Characteristics and problems of the design are discussed and the results are used to demonstrate an optimized conceptual design of a resonant DC/DC converter.:1 Einleitung 2 Theoretische Grundlagen 3 Ausführungsvarianten von MEMS-DC/DC-Wandlern 4 Designstudie und Umsetzung des resonanten Funktionsprinzips 5 Zusammenfassung und Ausblick

Predložená doktorandská dizertačná práca (ďalej len práca) sa zaoberá rozsiahlou analýzou valčekového hydrogenerátora s premenlivým geometrickým objemom a predikciou výkonových úspor dosiahnutých aplikáciou navrhnutého valčekového hydrogenerátora s premenlivým geometrickým objemom v hydrostatickom pohone vybraných mobilných pracovných strojov. Teoretický rozbor princípov fungovania valčekového hydrogenerátora a teória jednorozmerného simulačného modelu sú popísané v prvej časti práce. Na základe odvodenej teórie je vytvorený simulačný model, ktorý je vhodný na predikciu priebehu tlaku v komorách valčekového hydrogenerátora, síl pôsobiacich na valček a na predikciu vnútorných únikov vzniknutých skratovaním rozvodovej dosky, ktoré majú priamy vplyv na objemovú účinnosť valčekového hydrogenerátora. Simulačný model bol úspešne použitý pre optimalizáciu rozvodových dosiek valčekového hydrogenerátora a vhodnosť simulačného modelu potvrdili následné merania Práca obsahuje aj analýzu síl pôsobiacich na vodiaci prstenec, ktorej výsledky boli taktiež potvrdené meraním. Analýza týchto síl môže vylepšiť v konečnom dôsledku parametre budúcich tlakových regulácii. Práca ďalej obsahuje základné porovnanie použitých tlakových regulácii. Všetky uskutočnené merania potvrdili, že valčekový hydrogenerátor s premenlivým geometrickým objemom s testovanými tlakovými reguláciami je schopný úspešne pracovať v hydrostatickej prevodovke. Druhá časť práce analyzuje potenciál výkonových úspor valčekového hydrogenerátora s premenlivým geometrickým objemom pre dve mobilné aplikácie - teleskopický nakladač s hmotnosťou 9 ton a kombajn s hmotnosťou 20 ton. Analýza vyžaduje jednorozmerný simulačný model hydrostatického pohonu s teplotnou predikciou hydrostatickej prevodovky. Dva rozdielne koncepty variabilného doplňovacieho systému hydrostatickej prevodovky sú porovnané so štandardným doplňovacím systémom pre pracovný a transportný režim oboch vybraných typov vozidiel. Simulácia pohonu vozidla s valčekovým hydrogenerátorom s premenlivým geometrickým objemom vo funkcii doplňovacieho hydrogenerátora a obtokovou clonou potvrdili vyššie úspory iba v prípadoch, kedy rýchlosť doplňovacieho hydrogenerátora bola výrazne vyššia a prietok cez obtokovú clonu do skrine hlavného hydrogenerátora zabezpečil dostatočné chladenie. Najvyššie výkonové úspory boli dosiahnuté s premenlivým preplachovacím systémom, ktorého prietok sa menil podľa požiadaviek hydrostatickej prevodovky. Záver druhej časti práce sa zaoberá metodikou dimenzovania veľkosti doplňovacieho hydrogenerátora.

A digital system is often required to operate under a specific frequency. A ring oscillator can be helpful in this circumstance because it can generate a signal with a specific frequency. However, a ring oscillator is also sensitive to the environment temperature. With the increasing requirement of accuracy and stability, many approaches appear worldwide to make a temperature-insensitive ring oscillator. This thesis project presents an approach to compensate the temperature effect on a Current Starved Ring Oscillator(CSRO). More concretely, we researched how to achieve temperature compensation for CSRO in a digitally-controlled configuration. A Phase Frequency Detector (PFD) block is adapted to sense the frequency difference between the reference frequency and CSRO frequency. Two Charge Pumps (CP)are used to quantify the difference in voltage signal. A Dynamic Comparator block compares the signals from CPs. A following Bidirectional Counter block can count up or down to change the current in CSRO by a four-bit signal. In the end, the CSRO can generate an oscillating signal at the appropriate frequency after some adaptation time. This proposed circuit was realized with AMS 0.35 um CMOS technology and simulated using the Cadence tools. Power consumption, temperature compensation analysis and voltage supply compensation analysis under different temperatures are also performed in the project.