Abstract The developing trend toward the integreation of many function in application market of semiconductor, makes the original business model of IC design industry to change. From open structure (named ¡§Wintel¡¨ structure) till today, what we can see it shows as transition stage. It will be end in the situation the all devices can interlink to each other. All of us don¡¦t know how long we will overcome this transition stage. But it really challenges the orginal business model of IC design industry. The business model of IC design industry changes along with the changing in product application market. In this study, we do analysis of IC design industry¡¦s business model by four dimensions¡Xmarket strategies, capabilities of technology, the types of organization, financial resources. We will discuss the differents between Taiwan and American IC design industry In market strategy dimension, there are more and more difficults to distinguish between past strategy model including niche and volume strategies. Because the revolution of electronics application market, the better ways for Taiwan IC design industry to develop its market strategy are depending on capability focusing and the capture of market demend. When mentioning about the IC design skill, Taiwan IC design industry can choose several ways to cumulate its design capabilities according to the market strategy it chose. About types of the organization, the combination of fabless and fabless is the trend. Also 1¡¦st tier IDM will be the key roles who dominate the future IC industry. More than all, fabless who belong to system assembly factory or fabless who belong to foundry will be the mainstream in the IC industry and in electronics application market, too. Depending on what kinds of organzation IC design companies chose, it will affect the ability when they rising money. These four factors interaction built the business model of the Taiwan IC design industry.

Thesis: M.S., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 1977 / Bibliography : leaves 143-144. / M.S. / M.S. Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science

Thesis: Elec. E., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 1980 / Bibliography: leaf 96. / by Jeffrey Clay McHarg. / Elec. E. / Elec. E. Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science

No description available.

published_or_final_version / abstract / Electrical and Electronic Engineering / Master / Master of Philosophy

Areas which require high-temperature MOS circuits are instrumentations for geothermal and petroleum well-logging, space exploration, aero-propulsion systems, and other hostile environments. MOS digital circuits at high temperature are examined as well as the maximum operating temperature of MOS devices. Factors affecting high-temperature operation of these devices, including threshold voltage sensitivity, mobility degradation, leakage current characterization and interactions, zero-TC current in analog applications and reliability considerations, are discussed. Methods to reduce threshold voltage sensitivities, process modifications to reduce leakage current density at high temperature, circuit techniques to eliminate the leakage current effects, diode compensation, CMOS thermal latch-up and MOS scaling rules at high temperature are investigated. Experimental results of epitaxial diodes to verify the leakage current reduction effect are discussed.

This dissertation investigates the implementation of S-parameter based network techniques for the analysis of multiconductor, high speed VLSI integrated circuit and packaging interconnects. The S-parameters can be derived from three categories of input parameters: (1) lossy quasi-static R,L,C and G, (2) lossy frequency dependent (dispersive) R,L,C,G and (3) the propagation constants, Γ, the characteristic impedance, Z(c) and the conductor eigencurrents, I, derived from full wave analysis. The S-parameter network techniques developed allow for: the analysis of periodic waveform excitation, the incorporation of externally measured or calculated scattering parameter data and large system analysis through macro decomposition. The inclusion of non-linear terminations has also been developed.

Reducing circuit complexity to minimize design turnaround time and maximize chip area utilization is the most evident problem in dealing with VLSI layout. Three suggestions have been recommended to reduce circuit complexity. They are using regular modules as design targets, using hierarchical top-down design as a design methodology, and using CAD as a design tool. These three suggestions are the basis of this dissertation project. In this dissertation, three silicon compilers were implemented which take an universal AHPL circuit description as an input and automatically translate it into SLA (Storage Logic Array), PPLA (Path Programmable Logic Array), and ULA (Uncommitted Logic Array) chip layout. The goal is to study different layout algorithms and to derive better algorithms for alternative VLSI structures. In order to make a precise chip area comparison of these three silicon compilers, real SLA and ULA circuits have been designed. Four typical AHPL descriptions of different circuits or varying complexity were chosen as comparison examples. The result shows that the SLA layout requires least area for circuit realization generally. The PPLA approach is the worst one for large scale circuit realization, while the ULA lies in between.

Master of Science / Department of Biological & Agricultural Engineering / Naiqian Zhang / Permittivity is an important property of dielectric materials. By measuring the permittivity of a material, it is possible to obtain information about the material’s physical and chemical properties, which are of great importance to many applications. In this study, a realtime control system for a frequency-response (FR) permittivity sensor was developed. The core of the hardware was a kitCON167 microcontroller (PHYTEC America, LLC), which controlled and communicated with peripheral devices. The system consisted of circuits for waveform generation, signal conditioning, signal processing, data acquisition, data display, data storage, and temperature measurement. A C program was developed in the TASKING Embedded Development Environment (EDE) to control the system. The control system designed in this study embodied improvements over a previously designed version in the following aspects: 1) it used a printed circuit board (PCB); 2) the measurement frequency range was extended from 120 MHz to 400 MHz; 3) the resolution of measured FR data was improved by using programmable gain amplifiers; 4) a data storage module and a real-time temperature measurement module were added to the system; 5) an LCD display and a keypad were added to the system to display the FR data with corresponding frequencies and to allow users to enter commands. Impedance transformation models for the sensor probe, the coaxial cable that connects the control system with the sensor probe, and the signal processing circuit were studied in order to acquire information on the permittivity of measured materials from measured FR data. Coaxial cables of the same length terminated with different loads, including an open circuit, a short circuit, a 50 resistor, and a 50 resistor paralleled by a capacitor, were tested. The results indicated that the models were capable of predicting the impedances of these specific loads using the FR data. Sensor probes with different sizes and coaxial cables with two different lengths terminated with the same sensor probe were also tested. The results were discussed. Additional tests for the gain and phase detector were conducted to compare FR data measured by the gain and phase detector with those observed on an oscilloscope. The results were discussed.

Durant la dernière décennie, la miniaturisation des technologies de semi-conducteurs et de l’intégration à grande échelle a donné lieu à la conception de systèmes complexes, notamment l’intégration de plusieurs milliards de transistors sur un même die. Cette tendance pose de nombreux défis de fabrication et de fiabilité tels que la dissipation de puissance, la variabilité technologique et la polyvalence des applications. Les problèmes de fiabilité, représentées par la présence de points chauds thermiques peuvent accélérer la dégradation des transistors, et par conséquent réduire la durée de vie des puces, également appelée "vieillissement". Afin de relever ces défis, de nouvelles solutions sont nécessaires, basées notamment sur des systèmes auto-adaptatifs. Ces systèmes sont principalement composées d’une boucle de contrôle avec trois processus : (i) la surveillance, qui est chargée d’observer l’état du système, (ii) la prise de décision, qui analyse les informations collectées et prend des décisions pour optimiser le comportement du système et (iii) l’action qui ajuste les paramètres du système en conséquence. Cependant, une adaptation dépendre de façon critique sur le processus de suivi qui devrait fournir une estimation précise sur l’état du système de façon rentable. Dans cette thèse, nous étudions d’abord le suivi de la consommation d’énergie. Nous développons une méthode basée sur plusieurs algorithmes de fouille de données "data mining", pour surveiller l’activité de commutation sur quelques signaux pertinents sélectionnés au niveau RTL. La méthode proposée se compose d’un flot générique qui peut être utilisé pour modéliser la consommation d’énergie pour n’importe quel circuit RTL sur n’importe quelle technologie. Deuxièmement, nous améliorons le flot proposé pour estimer le comportement thermique globale de puce et de développer une nouvelle technique de placement des capteurs thermique sur puce. Les algorithmes proposés choisissent systématiquement le meilleur compromis entre la précision de l’observation et le coût représenté par le nombre de capteurs intégrés sur puce. La surface de la puce est décomposée en plusieurs zones thermiquement homogènes.Outre la partie conception, les systèmes embarqués modernes intègrent des capteurs matériels (analogiques ou numériques) qui peuvent être utilisés pour surveiller l’état du système. Ces méthodes industrielles sont généralement très coûteuses et nécessitent un grand nombre d’unités pour produire des informations précises avec une résolution à grain fin. Une solution alternative pour fournir une estimation précise de l’état du système est réalisée avec un ensemble de compteurs de performance qui peut être configuré pour effectuer le suivi des événements logiques à différents niveaux. Dans ce cas, nous proposons un nouvel algorithme pour la sélection des événements performance pertinents à partir des ressources locales, partagées et système. Nous proposons ensuite une implémentation d'un algorithme d'estimation basé sur un réseau neuronal. La méthode proposée est robuste contre les variations de température extérieure. En outre, estimation thermique est aussi peut être réalisé en utilisant les événements logiques actuelles et historiques, et la précision est évaluée sur la base de la profondeur dans le passé.Enfin, une fois la méthode de suivi et la cible définies et le système est configuré, la méthode de surveillance doit être utilisée au moment de "Run-time". Nous avons mis en place une boucle d’adaptation complète, avec un suivi dynamique de l’état du système afin atteindre une meilleure efficacité énergétique. / Over the last decade, the miniaturization of semiconductor technologies and the large-scale integration has given rise to complex system design, including the integration of several billions of transistors on a single die. This trend poses many manufacturing and reliability challenges such as power dissipation, technological variability and application versatility. The reliability issues represented by the presence of thermal hotspots can accelerate the degradation of the transistors, and consequently reduce the chip lifetime, also referred to as “aging”. In order to address these challenges, new solutions are required, based in particular on self-adaptive systems. Such systems are mainly composed of a control loop with three processes: (i) the monitoring, which is responsible for observing the state of the system, (ii) the diagnosis, which analyzes the information collected and makes decisions to optimize the behavior of the system, and (iii) the action that adjusts the system parameters accordingly. However, effective adaptations depend critically on the monitoring process that should provide an accurate estimation about the system state in a cost-effective manner. In this thesis, we firstly investigate the monitoring of the power consumption. We develop a method, based on several data mining algorithm, to monitor the toggling activity on a few relevant signals selected at the RTL level. The proposed method consists of a generic flow that can be used to model the power consumption for any RTL circuit on any technology. Secondly, we improve the proposed flow by estimating the overall chip thermal behavior and developing a new technique of on-die thermal sensor placement. The proposed algorithms systematically choose the best trade-off between accuracy and overhead. The surface of the chip is decomposed into several thermally homogeneous regions.Besides the design part, modern embedded systems integrates hardware sensors (analog or digital) that can be used to monitor the system’s state. These industrial methods are usually very expensive, and require a large number of units to produce precise information at a fine-grained resolution. An alternative solution to provide an accurate estimation of system’s state is achieved with a set of performance counters that can be configured to track logical events at different levels. To this end, we propose a novel algorithm for the selection of the relevant performance events from the local, shared and system resources. We propose then an implementation of a neural network based estimation algorithm. The proposed method is robust against the external temperature variations. Furthermore, thermal estimation is also can be achieved using the current and historic logical events, and the accuracy is evaluated on the basis of the depth in the past.Finally, once the tracking method and target are defined and the system is configured, the monitoring method should be used at “Run-time”. We implemented a complete adaptation loop, with a dynamic monitoring of the system’s state in order to achieve better energy efficiency.