Not available / text

Time-interleaved analog-to-digital converters make use of parallelization to increase the rate at which an analog signal can be digitized. Using M channels at their maximum sampling frequency allows for an overall sampling frequency of M times the individual converters' sampling rate. However, the performance of interleaved systems suffers from mismatches between the sub-converters. Offset mismatches, gain mismatches, and timing mismatches all contribute to the degradation of the resolution of the ADC system. Offset and gain mismatches can be corrected for in the digital domain with minimal extra processing. However, the effects of timing mismatches (specifically, the magnitude of the spurious tones that are introduced) are dependent on the frequency of the input, so digital correction is not a trivial task. This makes a circuit-based correction mechanism a much more desirable solution to the problem. This work explores the effect of timing mismatches on interleaved analog-to-digital converter performance. A set of requirements is derived to specify the performance of a variable-delay circuit for the tuning of sample clocks. Since the mismatches can be composed of both fixed and random components, several candidate architectures are modeled for their delay and jitter performance. One candidate is selected for design, based on its jitter performance and on practical considerations. A practical implementation of the clock-adjustment circuit is designed, featuring low-noise differential clock paths with high precision delay adjustment. A means of testing the circuit and verifying the precision of adjustment is presented. The design is implemented for fabrication, and post-layout simulations are shown to demonstrate the feasibility and functionality of the design.

We develop a new fully-automated transistor sizing tool for FPGAs that features area, delay and wire load modeling enhancements over prior work to improve its accuracy in advanced process nodes. We then use this tool to investigate a number of FPGA circuit design related questions in a 22nm process. We find that building FPGAs out of transmission gates instead of the currently dominant pass-transistors, whose performance and reliability are degrading with technology scaling, yields FPGAs that are 15% larger but are 10-25% faster depending on the allowable level of "gate boosting''. We also show that transmission gate FPGAs with a separate power supply for their gate terminal enable a low-voltage FPGA with 50% less power and good delay. Finally, we show that, at a possible cost in routability, restricting the portion of a routing channel that can be accessed by a logic block input can improve delay by 17%.

Major goal of this work is to develop, test and deploy algorithms for projecting electronic components onto a mechanical 3D object.

We develop a new fully-automated transistor sizing tool for FPGAs that features area, delay and wire load modeling enhancements over prior work to improve its accuracy in advanced process nodes. We then use this tool to investigate a number of FPGA circuit design related questions in a 22nm process. We find that building FPGAs out of transmission gates instead of the currently dominant pass-transistors, whose performance and reliability are degrading with technology scaling, yields FPGAs that are 15% larger but are 10-25% faster depending on the allowable level of "gate boosting''. We also show that transmission gate FPGAs with a separate power supply for their gate terminal enable a low-voltage FPGA with 50% less power and good delay. Finally, we show that, at a possible cost in routability, restricting the portion of a routing channel that can be accessed by a logic block input can improve delay by 17%.

This thesis presents the design and implementation of a current-mode computational CMOS image sensor that performs video image compression based on the CRVDC (conditional replenishment video data compression) algorithm. With such on-chip pre-processing, a compression ratio of 10:1 can be achieved without significant signal degradation. Our research focuses on designing the basic building blocks. As the image sensor works in the current-mode, the building blocks will be current mirrors and current comparators. Several kinds of current mirrors have been analyzed in details and an improved regulated cascode current mirror was chosen. Through simulations and prototyping, we demonstrated that this current mirror is capable of achieving a resolution of 11 bits at 200MHz. To implement the CRVDC algorithm, it was necessary to design an accurate and fast current comparator. Two novel CMOS current comparators were proposed and analyzed and the results were compared to conventional CMOS current comparators. Simulations and measurements demonstrated that the new CMOS current comparators had better performance both in terms of the propagation delay and power dissipation. For the CMOS image sensor, a photodiode-type active pixel transducer was used to convert incident light to photocurrent. The characterization and modeling of the transducer were presented and detailed analyses on the performance was obtained from chips fabricated using the standard 0.18μm CMOS process technology. Since the electrical characteristics of the active devices in the pixel sensor chip can generate large fixed pattern noise (FPN), a current-mode FPN suppression circuit was designed and adopted. Based on the test results obtained from a fabricated prototype chip, a FPN suppression rate of 0.35% was achieved. An on-chip analog to digital converter (ADC) was necessary to implement digital interface and a current-mode pipeline ADC with 8 bit resolution was proposed. Simulation results demonstrated that the ADC was monotonic and possessed an integral nonlinearity (INL) of ±0.45 LSB and a differential nonlinearity (DNL) of ±0.43 LSB. Our results suggested that the overall design can more than adequately meet the system specifications of the computational CMOS image sensor and potentially can be used as a front-end processing block in other image processing applications such as in motion detection and in image segmentation for a dynamic environment.

Thesis (M.S.)--University of Missouri--Rolla, 2007. / Vita. The entire thesis text is included in file. Title from title screen of thesis/dissertation PDF file (viewed November 26, 2007) Includes bibliographical references (p. 112-113).

Thesis (in competition for the Angas Engineering Scholarship)--University of Adelaide, 1948. / Typewritten copy.

Thesis (M. App. Sc.)--Carleton University, 2001. / Includes bibliographical references (p. 91-102). Also available in electronic format on the Internet.

Thesis (M. App. Sc.)--Carleton University, 2003. / Includes bibliographical references (p. 85-92). Also available in electronic format on the Internet.