M. Tech. (Chemical Engineering, Faculty of Engineering and Technology), Vaal University of Technology / Amplitude modulation is not commonly associated with effective amplifying. This work focuses on implementing amplitude modulation into a high efficiency Class E amplifier. Different types of amplifiers are compared with each other, to show the advantages of using a Class E amplifier. The theory of the Class E amplifier is dealt with in detail. A harmonic filter is designed for the amplifier to make it radio spectrum friendly. The modulation process is implemented with the aid of a transformer into the Class E amplifier. The advantage of this is that the transformer serves both as a radio frequency choke for the Class E circuit as well as a modulator. The implementation of the amplitude modulation into the high efficient Class E circuit was successful. The final Class E circuit had superb efficiency, the harmonic filter showed good harmonic attenuation and the modulation process had low distortion. All this resulted in a fine low power AM transmitter.

Ce travail porte sur l'étude d'un oscillateur de puissance contrôlé en tension en ondes millimétriques. L'objectif de la thèse est de concevoir cet oscillateur pour la bande de fréquence utilisée dans les standards IEEE 802.15.3c, IEEE 802.11ad et ECMA TC48, à savoir 56GHz-65GHz. Le principe de l'oscillateur de puissance est développé autour d'un amplificateur de puissance rebouclé pour engendrer un système oscillant. L'amplificateur de puissance développé est un amplicateur à deux étages. Celui de puissance est de classe E et le driver est de classe F. La boucle de retour est basée sur un vecteur-modulateur. Les circuits ont été fabriqués en technologie CMOS 65nm de STMicroelectronics. / This PhD thesis deals with a Power Voltage Controlled Oscillator (VCO) in millimeter waves. The aim is to design this Power VCO in the frequency band used in the standards IEEE 802.15.3c, IEEE 802.11ad and ECMA TC48, meaning from 56GHz to 65GHz. The principle of this oscillator is developed around a power amplifier in a loop, generating an oscillating system. The power amplifier is developed in a two-stage topology. The power stage is composed with a 60GHz class E cascoded amplifier and the driver stage is composed of a 60GHz class F amplifier. The feedback of the loop is based on a vector-modulator. The circuits have been realised in 65nm CMOS technology from STMicroelectronics.

While a lot of time and resources have been placed into transceiver design, due to the pace of a conventional engineering design process, the design of a power amplifier is often completed using scattered resources; and not always in a methodological manner, and frequently even by an iterative trial and error process. In this thesis, a research question is posed which enables for the investigation of the possibility of streamlining the design flow for power amplifiers. After thorough theoretical investigation of existing power amplifier design methods and modelling, inductors inevitably used in power amplifier design were identified as a major drawback to efficient design, even when examples of inductors are packaged in design HIT-Kits. The main contribution of this research is engineering of an inductor design process, which in-effect contributes towards enhancing conventional power amplifiers. This inductance search algorithm finds the highest quality factor configuration of a single-layer square spiral inductor within certain tolerance using formulae for inductance and inductor parasitics of traditional single-π inductor model. Further contribution of this research is a set of algorithms for the complete design of switch-mode (Class-E and Class-F) power amplifiers and their output matching networks. These algorithms make use of classic deterministic design equations so that values of parasitic components can be calculated given input parameters, including required output power, centre frequency, supply voltage, and choice of class of operation. The hypothesis was satisfied for SiGe BiCMOS S35 process from Austriamicrosystems (AMS). Several metal-3 and thick-metal inductors were designed using the abovementioned algorithm and compared with experimental results provided by AMS. Correspondence was established between designed, experimental and EM simulation results, enabling qualification of inductors other than those with experimental results available from AMS by means of EM simulations with average relative errors of 3.7% for inductors and 21% for the Q factor at its peak frequency. For a wide range of inductors, Q-factors of 10 and more were readily experienced. Furthermore, simulations were performed for number of Class-E and Class-F amplifier configurations with HBTs with ft greater than 60 GHz and total emitter area of 96 μm² as driving transistors to complete the hypothesis testing. For the complete PA system design (including inductors), simulations showed that switch-mode power amplifiers for 50 Ω load at 2.4 GHz centre frequency can be designed using the streamlined method of this research for the output power of about 6 dB less than aimed. This power loss was expected, since it can be attributed to non-ideal properties of the driving transistor and Q-factor limitations of the integrated inductors, assumptions which the computations of the routine were based on. Although these results were obtained for a single micro-process, it was further speculated that outcome of this research has a general contribution, since streamlined method can be used with a much wider range of CMOS and BiCMOS processes, when low-gigahertz operating power amplifiers are needed. This theory was confirmed by means of simulation and fabrication in 180 nm BiCMOS process from IBM, results of which were also presented. The work presented here, was combined with algorithms for SPICE netlist extraction and the spiral inductor layout extraction (CIF and GDSII formats). This secondary research outcome further contributed to the completeness of the design flow. All the above features showed that the routine developed here is substantially better than cut-and-try methods for design of power amplifiers found in the existing body of knowledge. / Thesis (PhD(Eng))--University of Pretoria, 2011. / Electrical, Electronic and Computer Engineering / unrestricted

Synthetic aperture sonar (SAS) is a wide-beam sonar technique commonly used for mapping the seafloor at high resolution. The Acoustics Research Group at the University of Canterbury operates a towed SAS system known as KiwiSAS-IV. This is currently being redesigned with the aim of reducing the weight, size and power requirements of the system. The long term goal is to make it capable of being mounted on an autonomous underwater vehicle (AUV) so that mapping of remote and/or dangerous waters can be accomplished without human interaction. This thesis presents the design of the front-end electronics used to drive the 36 transducers to produce the acoustic beam and receive the returning signals after they have reflected off a target. To achieve sufficient range, the transducers are driven with a 200 Vₚ₋ₚ signal with a maximum frequency of 110 kHz. This design uses class D switching amplifiers to generate these waveforms. The AD9271 integrated circuit, which can handle eight transducers simultaneously, is used to amplify the incoming signals and sample them at up to 50 MHz. This high sampling rate multiplied by all 36 transducers results in an amount of data which is too great for a conventional microprocessor-based system to handle. Instead, an FPGA is used to receive this data, decimate it using multiplier-free cascaded integrator-comb (CIC) filters, and then pass it to the back-end system for further processing and storage. A prototype circuit was created to test the theory developed in this thesis. This showed that the system is capable of generating the necessary waveforms and amplifying, capturing, and decimating the returning signals. However, further refinement is required before it is able to be used in the sonar system.

CMOS is the favorite candidate process for the high integration of the wireless communication IC blocks, RF frontend and digital baseband circuitry. Also the design of the RF power amplifier stage is the one of the most important part of the RF CMOS circuit design. Since high frequency and high power simultaneously exists on this stage, devices works on the limits of the process. Therefore standard device models may not be valid enough for a successful design. In the thesis high frequency passive device and MOS transistor models for the CMOS process searched though the literature and presented. Besides, different structures of the inductors are investigated for the best quality factor for the chosen process. Class E power amplifiers can reach very high efficiencies and they are very suitable for the low power applications. After the derivation of the classical Class E equations is presented, a new Class E circuit model including MOS transistor&rsquo / s channel resistance is developed and new sets of equations are obtained for the model. Circuit parameters are determined using numerical methods. Class E circuit simulations with these new parameters and earlier parameters are compared. Finally, a 100mW 2.4GHz Class E power amplifier is designed and simulated targeting Bluetooth applications. In this design, Class E circuit parameters are determined for AMS CMOS 0.35um process MOS transistor including the channel resistance. Simulations are performed using Cadence/BSIM3v3 and OrCad PSPICE.

Αντικείμενο αυτής της διπλωματικής υπήρξε η μελέτη μιας νέας μεθόδου ενίσχυσης ακουστικών συχνοτήτων, που μπορεί να αναπαράγει τον ήχο με την υψηλή ποιότητα των ενισχυτών τάξης Α και ταυτόχρονα με υψηλή απόδοση ισχύος, που χαρακτηρίζει τους ενισχυτές τάξης D. / This Diploma Thesis studies a new method of audio amplifying that can reproduce sound with both high fidelity as found in a class A amplifier and high efficiency which is characteristic of class D amplifier.

<p>Sal/Hall D, Forum, KTH-ICT, Isafjordsgatan 39, Kista</p>

Modern RF and millimeter-wave communication links call for high-efficiency front end systems with high output power and high linearity to meet minimum transmission requirements. Advanced modulation techniques, such as orthogonal frequency-division multiplexing (OFDM) require a large power amplifier (PA) dynamic range due to the high peak-to-average power ratio (PAPR). This thesis provides the analysis, design, and experimental verification of a high-efficiency, high-linearity S-band Doherty power amplifier (DPA) based on the Class F PA. Traditional Class F PAs use harmonically tuned output matching networks to obtain up to 88.4% power-added efficiency (PAE) theoretically, however the amplifier experiences poor linearity performance due to switched mode operation, typically yielding less than 30dB C/I ratio [1]. The DPA overcomes this linearity limitation by using an auxiliary amplifier to boost output power when the amplifier is subject to a high input power due to its limited conduction cycle. The DPA also provides improved saturated output power back-off performance to maintain high PAE during operation. The DPA presented in this thesis optimizes PAE while maintaining linearity by employing harmonically tuned Class F amplifier topology on a primary and an auxiliary amplifier. A Class F PA is first designed and fabricated to optimize output network linearity – this is followed by a DPA design based on the fabricated Class F PA. A GaN HEMT Class F PA and DPA operating at 2.2GHz are implemented with the PAs measuring 40% and 45% PAE respectively while maintaining a 30dB carrier-to-intermodulation (C/I) ratio on a two-tone test. The PAE is characterized at maximum 21dBm input power per tone and 20MHz tone spacing. When subject to a single 24dBm continuous wave input tone, the Class F PA and DPA output 37dBm and 35.5dBm respectively. The PAs presented in the thesis provide over 30dB C/I ratio up to 21dBm input tones while maintaining over 40% PAE suitable for base station applications.

abstract: Pulse Density Modulation- (PDM-) based class-D amplifiers can reduce non-linearity and tonal content due to carrier signal in Pulse Width Modulation - (PWM-) based amplifiers. However, their low-voltage analog implementations also require a linear- loop filter and a quantizer. A PDM-based class-D audio amplifier using a frequency-domain quantization is presented in this paper. The digital-intensive frequency domain approach achieves high linearity under low-supply regimes. An analog comparator and a single-bit quantizer are replaced with a Current-Controlled Oscillator- (ICO-) based frequency discriminator. By using the ICO as a phase integrator, a third-order noise shaping is achieved using only two analog integrators. A single-loop, singlebit class-D audio amplifier is presented with an H-bridge switching power stage, which is designed and fabricated on a 0.18 um CMOS process, with 6 layers of metal achieving a total harmonic distortion plus noise (THD+N) of 0.065% and a peak power efficiency of 80% while driving a 4-ohms loudspeaker load. The amplifier can deliver the output power of 280 mW. / Dissertation/Thesis / Ph.D. Electrical Engineering 2011

An investigation into performance improvements to the modulator stage of a class-D amplifier is conducted in this thesis. Two of the standard topologies, namely class-D open-loop pulse-width modulation (PWM), and the improved self-oscillating feedback system are benchmarked against a topology which includes both a hysteretic comparator in a feedback loop and triangle wave injection. Circuit performance is analyzed by comparing how the triangle injection circuit handles known issues with open-loop and self-oscillating circuits. Using this analysis, it is shown that the triangle injection topology offers an improved power supply rejection ratio relative to open-loop PWM and reduces distortion generated by frequency modulation characteristic of the self-oscillating topology.