We explore using pulsed latches for timing optimization -- a first in the academic FPGA community. Pulsed latches are transparent latches driven by a clock with a non-standard (i.e. not 50%) duty cycle. As latches are already present on commercial FPGAs, their use for timing optimization can avoid the power or area drawbacks associated with other techniques such as clock skew and retiming. We propose algorithms that automatically replace certain flip-flops with latches for performance gains. Under conservative short path or minimum delay assumptions, our latch-based optimization, operating on already routed designs, provides all the benefit of clock skew in most cases and increases performance by 9%, on average, essentially for "free". We show that short paths greatly hinder the ability of using pulsed latches, and further improvements in performance are possible by increasing the delay of certain short paths.

We explore using pulsed latches for timing optimization -- a first in the academic FPGA community. Pulsed latches are transparent latches driven by a clock with a non-standard (i.e. not 50%) duty cycle. As latches are already present on commercial FPGAs, their use for timing optimization can avoid the power or area drawbacks associated with other techniques such as clock skew and retiming. We propose algorithms that automatically replace certain flip-flops with latches for performance gains. Under conservative short path or minimum delay assumptions, our latch-based optimization, operating on already routed designs, provides all the benefit of clock skew in most cases and increases performance by 9%, on average, essentially for "free". We show that short paths greatly hinder the ability of using pulsed latches, and further improvements in performance are possible by increasing the delay of certain short paths.

Wireless networks become more and more important in modern information systems as the last mile/meter solutions, thanks to the flexibility of mobile access to facilitate Internet access anytime, anywhere. Given the limited resources, e.g., spectrum and energy supplies, to meet the ever increasing demand for wireless data services, new approaches are beckoned to enhance the spectrum and energy efficiency. We investigate this problem from three important aspects, digital modulation, clock synchronization and concurrent transmission scheduling. The contributions of this dissertation are four-fold. First, we employ the cross-layer design to explore the spatial diversity and broadcast nature of wireless links and propose a novel network modulation scheme that can superpose the information bits of different priorities into one symbol. It offers a new dimension to improve the network throughput since we can flexibly configure the transmission according to the channels among transceivers. Moreover, it is compatible with the main-stream hardware and we just need a software upgrade to implement the idea. Second, we propose modulation schemes based on hexagonal tiling, which is known to be the most compact way of two-dimensional regular tiling. In order to fully utilize the advantage of hexagonal constellation, we employ the non-binary error controlcoding since the number of constellation points of hexagonal constellation is not necessarily to be an integer power-of-two. The feasibility of these new modulation schemes is verified by the prototype system based on the software defined radio platform USRP2 and GNU Radio. Third, to facilitate a wide range of wireless communications technologies and protocols, clock synchronization among several wireless devices is a fundamental requirement. We investigated this problem by tracing to the source of clock desynchronization, which is the clock skew. However, as shown by measurement results, the clock skew is not constant and related to the working temperature. We propose a novel clock skew estimation algorithm that can leverage the temperature information to accurately estimate the clock skew. Based on the estimation results, we propose a clock synchronization scheme that can directly remove the clock skew according to the working temperature. Fourth, the traditional time-sharing based scheduling schemes usually schedule one transmission within certain area. The emerging broadband wireless devices can dynamically adjust the transmitted data rate according to the received signal to interference and noise ratio (SINR). Allowing concurrent transmissions may be more efficient, while optimal scheduling problem for concurrent transmissions is an NP-hard problem. We propose simple yet effective heuristic algorithms that can significantly improve the system throughput with moderate computational complexity. / Graduate / 0544 / yangzhe2007@gmail.com

abstract: Improving energy efficiency has always been the prime objective of the custom and automated digital circuit design techniques. As a result, a multitude of methods to reduce power without sacrificing performance have been proposed. However, as the field of design automation has matured over the last few decades, there have been no new automated design techniques, that can provide considerable improvements in circuit power, leakage and area. Although emerging nano-devices are expected to replace the existing MOSFET devices, they are far from being as mature as semiconductor devices and their full potential and promises are many years away from being practical. The research described in this dissertation consists of four main parts. First is a new circuit architecture of a differential threshold logic flipflop called PNAND. The PNAND gate is an edge-triggered multi-input sequential cell whose next state function is a threshold function of its inputs. Second a new approach, called hybridization, that replaces flipflops and parts of their logic cones with PNAND cells is described. The resulting \hybrid circuit, which consists of conventional logic cells and PNANDs, is shown to have significantly less power consumption, smaller area, less standby power and less power variation. Third, a new architecture of a field programmable array, called field programmable threshold logic array (FPTLA), in which the standard lookup table (LUT) is replaced by a PNAND is described. The FPTLA is shown to have as much as 50% lower energy-delay product compared to conventional FPGA using well known FPGA modeling tool called VPR. Fourth, a novel clock skewing technique that makes use of the completion detection feature of the differential mode flipflops is described. This clock skewing method improves the area and power of the ASIC circuits by increasing slack on timing paths. An additional advantage of this method is the elimination of hold time violation on given short paths. Several circuit design methodologies such as retiming and asynchronous circuit design can use the proposed threshold logic gate effectively. Therefore, the use of threshold logic flipflops in conventional design methodologies opens new avenues of research towards more energy-efficient circuits. / Dissertation/Thesis / Doctoral Dissertation Computer Science 2015

This work deals with the identification of a remote computer by monitoring TCP timestamps of the tracked device. It is possible to determine computer's clock skew from these timestamps as the clock skew is unique for every device. We are able to differentiate devices even though they have changed location, network address or connection type. Passive data capturing ensures that the identification process is invisible to the fingerprinted computer. It is necessary that the network communication of fingerprinted computer is visible to the observing device. We are able to utilise only TCP traffic with timestamps enabled.

Com o desenvolvimento da tecnologia CMOS, os circuitos estão ficando cada vez mais sujeitos a variabilidade no processo de fabricação. Variações estatísticas de processo são um ponto crítico para estratégias de projeto de circuitos para garantir um yield alto em tecnologias sub-100nm. Neste trabalho apresentamos uma técnica de medida on-chip para caracterizar violações de tempo de hold de flip-flops em caminhos lógicos curtos, que são geradas por incertezas de borda de relógio em projetos síncronos. Usando um circuito programável preciso de geração de skew de relógio, uma resolução de medida de ~1ps é alcançada para emular condições de corrida. Variações estatísticas de violações de tempo de hold são medidas em tecnologias CMOS de 130nm e 90nm para diversas configurações de circuitos, e também para diferentes condições de temperatura e Vdd. Essas violações são um ponto crítico em projetos grandes com milhares de caminhos curtos, pois se apenas um desses caminhos falhar, todo o circuito não vai funcionar em qualquer freqüência. Usando os resultados medidos, a variabilidade é dividida entre sistemática e randômica residual usando métodos matemáticos. Testes de normalidade são aplicados a estes dados para verificar de eles são Gaussianos normais ou não. A probabilidade de violações de tempo de hold considerando nossos resultados medidos e skews de relógio típicos é calculada, mostrando que o problema de violações de tempo de hold aumenta com o avanço da tecnologia. Finalmente, um algoritmo para proteger circuitos digitais contra violações de tempo de hold em caminhos curtos é apresentado. / With the shrinking of CMOS technology, the circuits are more and more subject to variability in the fabrication process. Statistical process variations are a critical issue for circuit design strategies to ensure high yield in sub-100nm technologies. In this work we present an on-chip measurement technique to characterize hold time violations of flip-flops in short logic paths, which are generated by clock-edge uncertainties in synchronous designs. Using a precise programmable clock-to-data skew generation circuit, a measurement resolution of ~1ps is achieved to emulate race conditions. Statistical variations of hold time violations are measured in a 130nm and 90nm lowpower CMOS technology for various register-to-register configurations, and also different conditions of temperature and Vdd. These violations are a critical issue in large designs with thousands of short paths, as if only one of these fails, the whole circuit will not work at any frequency. Using the measured results, the variability is divided between systematic and random residual using mathematical methods. Normality tests are applied to this data to check if they are normal Gaussians or not. The probability of hold time violations considering our measured data and typical clock skews is calculated, showing that the problem of hold time violations is increasing with technologic advances. Finally, an algorithm to protect digital circuits against hold time violations in short paths is presented.

Com o desenvolvimento da tecnologia CMOS, os circuitos estão ficando cada vez mais sujeitos a variabilidade no processo de fabricação. Variações estatísticas de processo são um ponto crítico para estratégias de projeto de circuitos para garantir um yield alto em tecnologias sub-100nm. Neste trabalho apresentamos uma técnica de medida on-chip para caracterizar violações de tempo de hold de flip-flops em caminhos lógicos curtos, que são geradas por incertezas de borda de relógio em projetos síncronos. Usando um circuito programável preciso de geração de skew de relógio, uma resolução de medida de ~1ps é alcançada para emular condições de corrida. Variações estatísticas de violações de tempo de hold são medidas em tecnologias CMOS de 130nm e 90nm para diversas configurações de circuitos, e também para diferentes condições de temperatura e Vdd. Essas violações são um ponto crítico em projetos grandes com milhares de caminhos curtos, pois se apenas um desses caminhos falhar, todo o circuito não vai funcionar em qualquer freqüência. Usando os resultados medidos, a variabilidade é dividida entre sistemática e randômica residual usando métodos matemáticos. Testes de normalidade são aplicados a estes dados para verificar de eles são Gaussianos normais ou não. A probabilidade de violações de tempo de hold considerando nossos resultados medidos e skews de relógio típicos é calculada, mostrando que o problema de violações de tempo de hold aumenta com o avanço da tecnologia. Finalmente, um algoritmo para proteger circuitos digitais contra violações de tempo de hold em caminhos curtos é apresentado. / With the shrinking of CMOS technology, the circuits are more and more subject to variability in the fabrication process. Statistical process variations are a critical issue for circuit design strategies to ensure high yield in sub-100nm technologies. In this work we present an on-chip measurement technique to characterize hold time violations of flip-flops in short logic paths, which are generated by clock-edge uncertainties in synchronous designs. Using a precise programmable clock-to-data skew generation circuit, a measurement resolution of ~1ps is achieved to emulate race conditions. Statistical variations of hold time violations are measured in a 130nm and 90nm lowpower CMOS technology for various register-to-register configurations, and also different conditions of temperature and Vdd. These violations are a critical issue in large designs with thousands of short paths, as if only one of these fails, the whole circuit will not work at any frequency. Using the measured results, the variability is divided between systematic and random residual using mathematical methods. Normality tests are applied to this data to check if they are normal Gaussians or not. The probability of hold time violations considering our measured data and typical clock skews is calculated, showing that the problem of hold time violations is increasing with technologic advances. Finally, an algorithm to protect digital circuits against hold time violations in short paths is presented.

Com o desenvolvimento da tecnologia CMOS, os circuitos estão ficando cada vez mais sujeitos a variabilidade no processo de fabricação. Variações estatísticas de processo são um ponto crítico para estratégias de projeto de circuitos para garantir um yield alto em tecnologias sub-100nm. Neste trabalho apresentamos uma técnica de medida on-chip para caracterizar violações de tempo de hold de flip-flops em caminhos lógicos curtos, que são geradas por incertezas de borda de relógio em projetos síncronos. Usando um circuito programável preciso de geração de skew de relógio, uma resolução de medida de ~1ps é alcançada para emular condições de corrida. Variações estatísticas de violações de tempo de hold são medidas em tecnologias CMOS de 130nm e 90nm para diversas configurações de circuitos, e também para diferentes condições de temperatura e Vdd. Essas violações são um ponto crítico em projetos grandes com milhares de caminhos curtos, pois se apenas um desses caminhos falhar, todo o circuito não vai funcionar em qualquer freqüência. Usando os resultados medidos, a variabilidade é dividida entre sistemática e randômica residual usando métodos matemáticos. Testes de normalidade são aplicados a estes dados para verificar de eles são Gaussianos normais ou não. A probabilidade de violações de tempo de hold considerando nossos resultados medidos e skews de relógio típicos é calculada, mostrando que o problema de violações de tempo de hold aumenta com o avanço da tecnologia. Finalmente, um algoritmo para proteger circuitos digitais contra violações de tempo de hold em caminhos curtos é apresentado. / With the shrinking of CMOS technology, the circuits are more and more subject to variability in the fabrication process. Statistical process variations are a critical issue for circuit design strategies to ensure high yield in sub-100nm technologies. In this work we present an on-chip measurement technique to characterize hold time violations of flip-flops in short logic paths, which are generated by clock-edge uncertainties in synchronous designs. Using a precise programmable clock-to-data skew generation circuit, a measurement resolution of ~1ps is achieved to emulate race conditions. Statistical variations of hold time violations are measured in a 130nm and 90nm lowpower CMOS technology for various register-to-register configurations, and also different conditions of temperature and Vdd. These violations are a critical issue in large designs with thousands of short paths, as if only one of these fails, the whole circuit will not work at any frequency. Using the measured results, the variability is divided between systematic and random residual using mathematical methods. Normality tests are applied to this data to check if they are normal Gaussians or not. The probability of hold time violations considering our measured data and typical clock skews is calculated, showing that the problem of hold time violations is increasing with technologic advances. Finally, an algorithm to protect digital circuits against hold time violations in short paths is presented.

The clock is the important synchronizing element in all synchronous digital systems. The difference in the clock arrival time between sink points is called the clock skew. This uncertainty in arrival times will limit operating frequency and might cause functional errors. Various clock routing techniques can be broadly categorized into 'balanced tree' and 'fixed mesh' methods. The skew and delay using the balanced tree method is higher compared to the fixed mesh method. Although fixed mesh inherently uses more wire length, the redundancy created by loops in a mesh structure reduces undesired delay variations. The fixed mesh method uses a single mesh over the entire chip but it is hard to introduce clock gating in a single clock mesh. This thesis deals with the introduction of 'reconfigurability' by using control structures like transmission gates between sub-clock meshes, thus enabling clock gating in clock mesh. By using the optimum value of size for PMOS and NMOS of transmission gate (SZF) and optimum number of transmission gates between sub-clock meshes (NTG) for 4x4 reconfigurable mesh, the average of the maximum skew for all benchmarks is reduced by 18.12 percent compared to clock mesh structure when no transmission gates are used between the sub-clock meshes (reconfigurable mesh with NTG =0). Further, the research deals with a ‘modified zero skew method' to connect synchronous flip-flops or sink points in the circuit to the clock grids of clock mesh. The wire length reduction algorithms can be applied to reduce the wire length used for a local clock distribution network. The modified version of ‘zero skew method’ of local clock routing which is based on Elmore delay balancing aims at minimizing wire length for the given bounded skew of CDN using clock mesh and H-tree. The results of ‘modified zero skew method' (HC_MZSK) show average local wire length reduction of 17.75 percent for all ISPD benchmarks compared to direct connection method. The maximum skew is small for HC_MZSK in most of the test cases compared to other methods of connections like direct connections and modified AHHK. Thus, HC_MZSK for local routing reduces the wire length and maximum skew.

The rapid growth of the Internet and the proliferation of its new applications pose a serious challenge in network performance management and monitoring. The current Internet has no mechanism for providing feedback on network congestion to the end-systems at the IP layer. For applications and their end hosts, end-to-end measurements may be the only way of measuring network performance. Understanding the packet delay and loss behavior of the Internet is important for proper design of network algorithms such as routing and flow control algorithms, for the dimensioning of buffers and link capacity, and for choosing parameters in simulation and analytic studies. In this thesis, round trip time (RTT), one-way network delay and packet loss in the Internet are measured at different times of the day, using a Voice over IP (VoIP) device. The effect of clock skew on one-way network delay measurements is eliminated by a Linear Programming algorithm, implemented in MATLAB. Distributions of one-way network delay and RTT in the Internet are determined. It is observed that delay distribution has a gamma-like shape with heavy tail. It is tried to model delay distribution with gamma, lognormal and Weibull distributions. It is observed that most of the packet losses in the Internet are single packet losses. The effect of firewall on delay measurements is also observed.