Today’s microprocessors with millions of transistors perform high-complexity computing at multi-gigahertz clock frequencies. The ever-increasing chip size and speed call for new methodologies in clock distribution network. Conventional global synchronization techniques exhibit many drawbacks in the advanced VLSI chips such as high-speed microprocessors. A significant percentage of the total power consumption in a microprocessor is dissipated in the clock distribution network. Also since the chip dimensions increase, clock skew management becomes very challenging in the framework of conventional methodology. Long interconnect delays limit the maximum clock frequency and become a bottleneck for future microprocessor design. In such a situation, new alternative techniques for synchronization in system-on-chip are demanded. This thesis presents new alternatives for traditional clocking and synchronization methods, in which, speed and power consumption bottlenecks are treated. For this purpose, two new techniques based on mesochronous synchronization and resonant clocking are investigated. The mesochronous synchronization technique deals with remedies for skew and delay management. Using this technique, clock frequency up to 5 GHz for on-chip communication is achievable in 0.18-μm CMOS process. On the other hand the resonant clocking solves significant power dissipation problem in the clock network. This method shows a great potential in power saving in very large-scale integrated circuits. According to measurements, 2.3X power saving in clock distribution network is achieved in 130-nm CMOS process. In the resonant clocking, oscillator plays a crucial role as a clock generator. Therefore an investigation about oscillators and possible techniques for jitter and phase noise reduction in clock generators has been done in this research framework. For this purpose a study of injection locking phenomenon in ring oscillators is presented. This phenomenon can be used as a jitter suppression mechanism in the oscillators. Also a new implementation of the DLL-based clock generators using ring oscillators is presented in 130-nm CMOS process. The measurements show that this structure operates in the frequency range of 100 MHz-1.5 GHz, and consumes less power and area compared to the previously reported structures. Finally a new implementation of a 1.8-GHz quadrature oscillator with wide tuning range is presented. The quadrature oscillators potentially can be used as future clock generators where multi-phase clock is needed. / Report code: LiU-TEK-LIC-2006:22

Computer memories now play a key role in our everyday life given the increase in the number of connected smart devices and wearables. Recently post-CMOS memory technologies are gaining significant research attention along with the regular ones. Spin Transfer Torque Magnetoresistive RAM (STT-MRAM) is one such post-CMOS memory technology with a rapidly growing commercial interest and potential across diverse application platforms. Research has shown the ability of STT-MRAM to replace different levels of memory hierarchy as well. In brief, STT-MRAM possesses all the favorable properties of a universal memory technology. In this dissertation we have explored the roles of this emerging memory technology beyond traditional storage. The purpose is to enhance the overall performance of the application platform that STT-MRAM is a part of. The roles that we explored are computation and security. We have discussed how the intrinsic properties of STT-MRAM can be used for computation and authentication. The two properties that we are interested in are the dipolar coupling between the magnetic memory cells and the variations in the geometries of the memory cell. Our contributions here are a 22nm CMOS integrated STT-MRAM based logic-in-memory architecture and a geometric variation based STT-MRAM signature generation. In addition we have explored the device physics and the dynamics of STT-MRAM cells to propose a STT based clocking mechanism that is friendlier with the logic-in-memory setup. By investigating the logic layouts and propagation style in the architecture, we have also proposed different techniques that can improve the logic density and performance of the architecture.

<p>This thesis deals with the study and comparison of on-chip LC Oscillators, used in energy recovery clocking, in terms of Power, Area of Inductor and change in load capacitance. Simulations show how the frequency of the two oscillators varies when the load capacitance is changed from 5pF to 105pF for a given network resistance. A conventional driver is used as a reference for comparisons of power consumptions of the two oscillators. It has been shown that the efficiency of the two oscillators can exceed that of a conventional driver provided the distribution network resistance is low and the on-chip inductor has a high enough Q value. Conclusions drawn from the simulations, using network resistances varying from 0Ω to 4Ω, show that the selection of the oscillator would depend on the network resistance and the amount of area available for the inductors.</p>

<p>The impressive evolution of modern high-performance microprocessors have resulted in chips with over one billion transistors as well as multi-GHz clock frequencies. As the silicon integrated circuit industry moves further into the nanometer regime, three of the main challenges to overcome in order for continuing CMOS technology scaling are; growing standby power dissipation, increasing variations in process parameters, and increasing power dissipation due to growing clock load and circuit complexity. This thesis addresses all three of these future scaling challenges with the overall focus on reducing the total clock-power for low-power, multi-GHz VLSI circuits.</p><p>Power-dissipation related to the clock generation and distribution is identified as the dominating contributor of the total active power dissipation. This makes novel power reduction techniques crucial in future VLSI design. This thesis describes a new energy-recovering clocking technique aimed at reducing the total chip clock-power. The proposed technique consumes 2.3x lower clock-power compared to conventional clocking at a clock frequency of 1.56 GHz.</p><p>Apart from increasing power dissipation due to leakage also the robustness constraints for circuits are impacted by the increasing leakage. To improve the leakage robustness for sub-90 nm low clock load dynamic flip-flops a novel keeper technique is proposed. The proposed keeper utilizes a scalable and simple leakage compensation technique. During any low frequency operation, the flip-flop is configured as a static flip-flop with increased functional robustness.</p><p>In order to compensate the impact of the increasingly large process variations on latches and flip-flops, a reconfigurable keeper technique is presented in this thesis. In contrast to the traditional design for worst-case process corners, a variable keeper circuit is utilized. The proposed reconfigurable keeper preserves the robustness of storage nodes across the process corners without degrading the overall chip performance.</p> / Report code: LiU-TEK-LIC-2006:21.

ElectroMagnetic Interferences (EMI) are emerging problems in today's high speed circuits. There are several examples that these interferences affected the circuits and systems. This work tries to reduce the abovementioned problems in synchronous systems by modifying the clock signal such that it produces less interferers. In this thesis first EMI and its sources and related definitions are studied in Chap.1 and then a theoretical background is presented in Chap.2, finally Chap.3 and Chap.4 are dedicated to circuit implementation and simulation results, respectively. A novel multi-segment clocking scheme is presented in this thesis. An analytical methods for formal verification of advantages of this clocking method is presented in Chap.2. Chap.3 and Chap.4 also are devoted to implementation, simulation and comparison of proposed clocking method versus other methods. Since proposed clocking method does not set any constraint on timing (speed of the circuit) and does not impose very high extra power consumption on the circuit, compared to the conventional clocking, this method could be used to reduce interferences in system.

This thesis deals with the study and comparison of on-chip LC Oscillators, used in energy recovery clocking, in terms of Power, Area of Inductor and change in load capacitance. Simulations show how the frequency of the two oscillators varies when the load capacitance is changed from 5pF to 105pF for a given network resistance. A conventional driver is used as a reference for comparisons of power consumptions of the two oscillators. It has been shown that the efficiency of the two oscillators can exceed that of a conventional driver provided the distribution network resistance is low and the on-chip inductor has a high enough Q value. Conclusions drawn from the simulations, using network resistances varying from 0Ω to 4Ω, show that the selection of the oscillator would depend on the network resistance and the amount of area available for the inductors.

No description available.

Les études expérimentales et numériques suivantes visent à la compréhension profonde de l’écoulement se développant dans le compresseur haute-vitesse axial de 3.5 étages CREATE, étudié sur un banc d’essai de 2 MW au Laboratoire de Mécanique des Fluides et Acoustique (LMFA) à Lyon, France. Ce travail a trois objectifs principaux : D’abord, une description globale de l’écoulement avec une identification des limites aux méthodes d’exploration utilisées ; Ensuite, la caractérisation de l’effet du clocking stator-stator dans un compresseur à haute-vitesse ; Troisièmement, l’identification des instabilités à faibles débits pour confirmer les études sur les compresseurs à basse-vitesse et contribuer à plus de compréhension.Il est montré qu’une mauvaise interprétation des données de performance stationnaire se fait facilement en raison des contraintes de mesure et des coefficients de correction sont proposés. À certains endroits dans le compresseur, des limites aux méthodes d’exploration (expérimentales et numériques) de l’écoulement sont identifiées. Cette identification va permettre la poursuite du développement des méthodes. Les principales erreurs de prédiction des simulations concernent la surestimation du blocage induit par l’écoulement de jeu et l’augmentation de pression. En outre, les mesures fournies par les sondes de pression pneumatique surestiment la pression statique en amont des stators. Cette erreur est probablement provoquée par l’interaction entre le champ potentiel du stator et la sonde elle-même. De plus, l’anémométrie Doppler laser surestime la vitesse en aval des stators. Le transport des sillages du rotor à travers des stators n’est pas correctement capturé avec les particules d’ensemencement.Le clocking a seulement un petit effet global dans la bande d’incertitude de mesure dans ce compresseur. Plusieurs contributions à ce faible effet de clocking sont identifiées par l’analyse du transport des structures d’écoulement : Le mélange circonférentiel du sillage de stator et la déformation des sillages le long de leur trajet dans l’écoulement. L’effet local du clocking dépend de la hauteur de veine en raison de la variation de la forme des aubages et du transport des sillages. Des effets positifs et négatifs sont présentés, qui globalement se compensent dans ce compresseur. Les instabilités dans ce compresseur dépendent du point de fonctionnement et des méthodes d’exploration de l’écoulement. Aux points de fonctionnement stables et à la vitesse nominale du compresseur, les résultats numériques montrent une perturbation tournante dans les rotors 2 et 3, alors que les mesures montrent une perturbation tournante que dans le premier rotor et seulement à basse vitesse du compresseur. Dans les deux cas, les perturbations montrent des caractéristiques semblables. Une étude numérique permet d’exclure l’influence des interactions rotor-stator sur la perturbation tournante et met en évidence sa source. Des nouvelles connaissances sur le comportement stable et la périodicité du rotating instability (mesuré) sont dérivées contrairement au comportement instable suggéré par la dénomination et la littérature. Il est montré que cette perturbation évolue en cellule de décrochage tournante à l’approche de la limite de stabilité. A la vitesse nominale du compresseur, une entrée en instabilités de type spike est identifiée expérimentalement. Une description précise de l’apparition brutale du spike et sa différence par rapport à une cellule de décollement tournant sont présentées. / The following experimental and numerical investigations aim at the deep understanding of the flow field in the 3.5 stages high-speed axial compressor CREATE, studied on a 2 MW test rig at the Laboratory of Fluid Mechanics and Acoustics (LMFA) in Lyon, France. This work focuses on three major objectives: Firstly, a global description of the flow field with an identification of limitations to the used exploration methods; Secondly, the characterization of the effect of stator-stator clocking in a high-speed compressor; Thirdly, the identification of instabilities arising at low mass flow rates for confirming studies on low-speed compressors and giving new insights.This work demonstrates that a mis-interpretation of steady performance data occurs easily due to measurement constraints and correction coefficients are proposed. At certain locations in the compressor, the flow field exploration (experimental and numerical) methods are identified to be challenged. This identification will initiate further development of the methods. The main mis-predictions of the simulations concern the over-prediction of the blockage induced by the tip leakage flow and eventually an over-predicted pressure rise. Furthermore, the measurements provided by the pneumatic pressure probes over-estimate the static pressure upstream of the stators. This error is induced by the interaction between the stator potential field and the probe it-self. In addition, the laser Doppler anemometry method over-estimates the velocity downstream the stators. The transport of the rotor wakes through the stators might not be correctly captured with the seeding particles in this high-speed compressor.The investigation of the stator clocking reveals only a small global effect within the measurement uncertainty band. Several contributions to the weak effect of clocking are identified by analysis of the flow structure transport, namely the time-mean mixing out of the stator wakes and the deformation of wakes along their flow path. The local effect of clocking depends on the span-height because of the variation of the circumferential position of the stator wakes and the stator blade shape over the span-height. Local possible positive and negative effects of clocking are identified and are shown to be almost in balance in this compressor. Furthermore, this work demonstrates that the unsteadiness in the flow field is not linked conclusively to the stator clocking.In this compressor, the arising instabilities depend on the operating point and flow field exploration methods. At stable operating points and nominal compressor speed, the numerical results reveal a rotating disturbance in the rotors 2 and 3, whereas the measurements show a rotating disturbance only in the first rotor and only at part speed. In both cases the disturbance exhibits rotating instability like characteristics. An exhaustive numerical study allows to exclude the commonly assumed influence of rotor-stator interactions on the rotating disturbance and pinpoints its source. New insights into the stable behavior and periodicity of the measured rotating instability are derived contrary to the unstable behavior suggested by the naming and literature. This disturbance is shown to evolve into rotating stall cells when approaching the stability limit. At nominal compressor speed, a spike type surge inception is identified I n the measured field. A precise description of the abrupt onset of the spike cell and its difference to a rotating stall cell are presented.

La Peste porcine africaine (PPA) est une maladie contagieuse spécifique du porc domestique due au seul arbovirus à ADN identifié à ce jour. Décrite pour la première fois en 1921 au Kenya, la maladie a ensuite diffusé dans de nombreuses régions du monde. Malgré l'isolement de nombreuses souches virales au cours du temps, peu d'études phylogénétiques ont été menées jusqu'ici pour comprendre les relations unissant ces isolats entre eux. Or, la caractérisation est essentielle à la traçabilité des souches et donc à la compréhension de l'épidémiologie de la maladie. De plus, les conditions climatiques et environnementales des principaux pays atteints rendent difficile l'accès, le transport et la conservation de nouvelles souches. Dans cette thèse, un protocole de prélèvement et de conservation du sang a été développé, pour la détection et la caractérisation rapides des souches. Une étude phylogénétique approfondie a été réalisée en utilisant des données de séquences publiques et inédites de virus isolés depuis 1950. Les analyses ont porté sur les gènes B646L, CP204L et E183L. Les analyses phylogénétiques ont utilisé les méthodes de maximum de vraisemblance et d'inférence bayésienne, qui ont permis de proposer une nouvelle nomenclature virale en 35 clusters différents. De plus, une datation des origines du virus a été menée, après avoir éliminé les biais d'analyse dus à une pression de sélection positive et/ou aux recombinaisons. L'horloge moléculaire a permis de déterminer que l'ancêtre commun le plus proche des souches contemporaines (TMRCA) se situait au début du 18ème siècle. / African swine fever (ASF) is a highly lethal disease of domestic pigs caused by the only known DNA arbovirus. It was first described in Kenya in 1921 and since then a substantial number of isolates have been collected worldwide. However, only few phylogenetic studies have been carried out to better understand the relationships between isolates, which is essential for virus traceability and epidemiological understanding of the disease. Access, transport and virus conservation are also complicated by climatic and environmental conditions in affected developing countries. In this thesis, a simple method of blood sampling was developed allowing rapid virus detection and characterization. Comprehensive phylogenetic reconstructions were made using publicly and newly generated sequences of hundreds ASFV isolates of the last 60 years. Analyses focused on B646L, CP204L and E183L genes. Phylogenetic analyses were achieved using maximum likelihood and Bayesian coalescence methods and a new lineage based nomenclature is proposed to designate 35 different clusters. In addition, dating of ASFV origin was carried out from the molecular data sets. To avoid biased diversity, positive selection or recombination events were neutralized. The molecular clock analyses revealed that ASFV strains currently circulating have evolved over 300 years, with a time to the most recent common ancestor (TMRCA) going back to the early 18th century.

Semiconductor industry seems to approach a wall where physical geometry and power density issues could possibly render the device fabrication infeasible. Quantum-dot Cellular Automata (QCA) is a new nanotechnology that claims to offer the potential of manufacturing even denser integrated circuits, which can operate at high frequencies and low power consumption. In QCA technology, the signal propagation occurs as a result of electrostatic interaction among the electrons as opposed to flow to the electrons in a wire. The basic building block of QCA technology is a QCA cell which encodes binary information with the relative position of electrons in it. A QCA cell can be used either as a wire or as logic. In QCA, the directionality of the signal flow is controlled by phase-shifted electric field generated on a separate layer than QCA cell layer. This process is called clocking of QCA circuits. The logic realization using regular structures such as PLAs have played a significant role in the semiconductor field due to their manufacturability, behavioral predictability and the ease of logic mapping. Along with these benefits, regular structures in QCA's would allow for uniform QCA clocking structure. The clocking structure is important because the pioneers of QCA technology propose it to be fabricated in CMOS technology. This thesis presents a detailed design implementation and a comparative analysis of logic realization using regular structures, namely Shannon-Lattices and PLAs for QCAs. A software tool was developed as a part of this research, which automatically generates complete QCA-Shannon-Lattice and QCA-PLA layouts for single-output Boolean functions based on an input macro-cell library. The equations for latency and throughput for the new QCA-PLA and QCA-Shannon-Lattice design implementations were also formulated. The correctness of the equations was verified by performing simulations of the tool-generate layouts with QCADesigner. A brief design trade-off analysis between the tool-generated regular structure implementation and the unstructured custom layout in QCA is presented for the full-adder circuit.