An intelligent camera includes a processor, which can extract information from images without the need for an external processing unit, and interface devices used to make the results available to other devices. This paper describes the intelligent camera design and implementation into the Field Programmable Gate Array (FPGA). The implemented architecture contains a camera controller, a memory controller, an IIC controller, a VGA controller, and an execution unit. The camera controller communicates with a CMOS chip. The memory controller communicates with a DDR SDRAM memory. The IIC controller is the interface between a PLB bus and an IIC bus. The VGA controller takes data from the memory and transform them into the VGA format (640x480, 60 Hz). The execution unit extracts the image data from the memory. These data are processed by hardware pixel by pixel, which results in a modified image. The camera units has been implemented in the VHDL and Verilog languages.

Le projet de thèse porte sur l'oscillateur harmonique; l'oscillateur dépend du signal de fréquence fondamentale à 25 GHz, qui est amplifié à l'aide d'un LNA et d'un amplificateur de puissance afin de générer un troisième signal harmonique à 75 GHz en sortie et de faire une contre-réaction du signal fondamental afin d'assurer la continuité de l'oscillation. Un diplexeur est utilisé pour séparer les deux fréquences à l’étage de sortie, en tenant compte de l’amélioration de la puissance de sortie, du bruit de phase et de l’efficacité de puissance ajoutée PAE à la fréquence candidate de l’application 5G. La technologie de transistor choisie est le FDSOI 28 nm de STMicroelectronics. / The PhD project is about harmonic oscillator; the oscillator depends on the fundamental frequency signal at 25 GHz which is amplified using an LNA and power amplifier in order to generate third harmonic signal at 75 GHz at the output, and feedback the fundamental signal to ensure the continuity of the oscillation. A diplexer is used to separate between both frequencies at the output stage, taking in consideration the improvement of the output power, phase noise, and the power added efficiency PAE at the candidate frequency of 5G application. The transistor technology chosen is the 28nm FDSOI from the STMicroelectronics.

Ce travail de thèse a porté sur des problèmes de fiabilité de circuits intégrés en technologie CMOS 65 nm, en particulier sur la conception en vue de la fiabilité, la simulation et l'amélioration de la fiabilité. Les mécanismes dominants de vieillissement HCI et NBTI ainsi que la variation du processus ont été étudiés et évalués quantitativement au niveau du circuit et au niveau du système. Ces méthodes ont été appliquées aux modulateurs Sigma-Delta afin de déterminer la fiabilité de ce type de composant qui est très utilisé. / This thesis concentrates on reliability-aware methodology development, reliability analysis based on simulation as well as failure prediction of CMOS 65nm analog and mixed signal (AMS) ICs. Sigma-Delta modulators are concerned as the object of reliability study at system level. A hierarchical statistical approach for reliability is proposed to analysis the performance of Sigma-Delta modulators under ageing effects and process variations. Statistical methods are combined into this analysis flow.

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The facility to capture the arrival of a single photon, is the fundamental limit to the detection of quantised electromagnetic radiation. An image sensor capable of capturing a picture with this ultimate optical and temporal precision is the pinnacle of photo-sensing. The creation of high spatial resolution, single photon sensitive, and time-resolved image sensors in complementary metal oxide semiconductor (CMOS) technology offers numerous benefits in a wide field of applications. These CMOS devices will be suitable to replace high sensitivity charge-coupled device (CCD) technology (electron-multiplied or electron bombarded) with significantly lower cost and comparable performance in low light or high speed scenarios. For example, with temporal resolution in the order of nano and picoseconds, detailed three-dimensional (3D) pictures can be formed by measuring the time of flight (TOF) of a light pulse. High frame rate imaging of single photons can yield new capabilities in super-resolution microscopy. Also, the imaging of quantum effects such as the entanglement of photons may be realised. The goal of this research project is the development of such an image sensor by exploiting single photon avalanche diodes (SPAD) in advanced imaging-specific 130nm front side illuminated (FSI) CMOS technology. SPADs have three key combined advantages over other imaging technologies: single photon sensitivity, picosecond temporal resolution and the facility to be integrated in standard CMOS technology. Analogue techniques are employed to create an efficient and compact imager that is scalable to mega-pixel arrays. A SPAD-based image sensor is described with 320 by 240 pixels at a pitch of 8μm and an optical efficiency or fill-factor of 26.8%. Each pixel comprises a SPAD with a hybrid analogue counting and memory circuit that makes novel use of a low-power charge transfer amplifier. Global shutter single photon counting images are captured. These exhibit photon shot noise limited statistics with unprecedented low input-referred noise at an equivalent of 0.06 electrons. The CMOS image sensor (CIS) trends of shrinking pixels, increasing array sizes, decreasing read noise, fast readout and oversampled image formation are projected towards the formation of binary single photon imagers or quanta image sensors (QIS). In a binary digital image capture mode, the image sensor offers a look-ahead to the properties and performance of future QISs with 20,000 binary frames per second readout with a bit error rate of 1.7 x 10-3. The bit density, or cumulative binary intensity, against exposure performance of this image sensor is in the shape of the famous Hurter and Driffield densitometry curves of photographic film. Oversampled time-gated binary image capture is demonstrated, capturing 3D TOF images with 3.8cm precision in a 60cm range.

<p><p>During later years communication schemes for handheld devices have increased in complexity due to the desire to increase the throughput, i.e. the amount of information sent over a medium simultaneously. Increasing throughput can be accomplished, not only by modulating the phase or frequency, but also the amplitude. This leads to tougher requirements on the power amplifier. The conventional power amplifiers, which have the ability to follow the envelope of the carrier, are inefficient. This thesis aims to compare two old but revived architectures which exploit high-efficiency amplifiers and still have a linear relationship between the input and output. The architectures; the Polar Linearization Technique and Outphasing share the same foundation. Based on literature, the polar technique have been more successful of employing examples fufilling communication standards. The polar technique is also more versatile regarding power combiners, distortion correction and alternative implementations. The simulations performed in this thesis results show that the polar amplifier is less sensitive to process variations and has higher maximum efficiency. On the other hand, the outphasing topology have the highest linearity figures.</p></p>

With the rapid development of information technology, more and more bandwidth is required to transmit multimedia data. Since local communication networks are moving to wireless domain, it brings up great challenges for making integrated wideband wireless front-ends suitable for these applications. RF filtering is a fundamental need in all wireless front-ends and is one of the most difficult parts to be integrated. This has been a major obstacle to the implementation of low power and low cost integrated wireless terminals. <p> Lots of previous work has been done to make integrated RF filters applicable to these applications. However, some of these filters are not designed with standard CMOS technology. Some of them are not designed in desired frequency bands and others do not have sufficient frequency bandwidth. This research demonstrates the design of a tunable wideband RF filter that operates at 3.6 GHz and can be easily changed to a higher frequency range up to 5 GHz. This filter is superior to the previous designs in the following aspects: a) wider bandwidth, b) easier to tune, c) balancing in noise and linearity, and d) using standard CMOS technology. The design employs the state-of-the-art inductor degenerated LNA, acting as a transconductor to minimize the overall noise figure. A Q-enhancement circuit is employed to compensate the loss from lossy on-chip spiral inductors. Center frequency and bandwidth tuning circuits are also embedded to make the filter suitable for multi band operations. <p> At first, a second order bandpass filter prototype was designed in the standard 0.18 ìm CMOS process. Simulation results showed that at 3.6 GHz center frequency and with a 60-MHz bandwidth, the input third-order intermodulation product (IIP3) and input-referred 1 dB compression point (P1dB) was -22.5 dBm and -30.5 dBm respectively. The image rejection at 500 MHz away from the center frequency was 32 dB (250 MHz intermediate frequency). The Q of the filter was tunable over 3000 and the center frequency tuning range was about 150 MHz. <p> By cascading three stages of second order filters, a sixth order filter was designed to enhance the image rejection ability and to extend the filter bandwidth. The sixth order filter had been fabricated in the standard 0.18 ìm CMOS process using 1.8-V supply. The chip occupies only 0.9 mm 0.9 mm silicon area and has a power consumption of 130-mW. The measured center frequency was tunable from 3.54 GHz to 3.88 GHz, bandwidth was tunable from 35 MHz to 80 MHz. With a 65 MHz bandwidth, the filter had a gain of 13 dB, an IIP3 of -29 dBm and a P1dB of -46 dBm.