With the rapid development of information technology, more and more bandwidth is required to transmit multimedia data. Since local communication networks are moving to wireless domain, it brings up great challenges for making integrated wideband wireless front-ends suitable for these applications. RF filtering is a fundamental need in all wireless front-ends and is one of the most difficult parts to be integrated. This has been a major obstacle to the implementation of low power and low cost integrated wireless terminals. <p> Lots of previous work has been done to make integrated RF filters applicable to these applications. However, some of these filters are not designed with standard CMOS technology. Some of them are not designed in desired frequency bands and others do not have sufficient frequency bandwidth. This research demonstrates the design of a tunable wideband RF filter that operates at 3.6 GHz and can be easily changed to a higher frequency range up to 5 GHz. This filter is superior to the previous designs in the following aspects: a) wider bandwidth, b) easier to tune, c) balancing in noise and linearity, and d) using standard CMOS technology. The design employs the state-of-the-art inductor degenerated LNA, acting as a transconductor to minimize the overall noise figure. A Q-enhancement circuit is employed to compensate the loss from lossy on-chip spiral inductors. Center frequency and bandwidth tuning circuits are also embedded to make the filter suitable for multi band operations. <p> At first, a second order bandpass filter prototype was designed in the standard 0.18 ìm CMOS process. Simulation results showed that at 3.6 GHz center frequency and with a 60-MHz bandwidth, the input third-order intermodulation product (IIP3) and input-referred 1 dB compression point (P1dB) was -22.5 dBm and -30.5 dBm respectively. The image rejection at 500 MHz away from the center frequency was 32 dB (250 MHz intermediate frequency). The Q of the filter was tunable over 3000 and the center frequency tuning range was about 150 MHz. <p> By cascading three stages of second order filters, a sixth order filter was designed to enhance the image rejection ability and to extend the filter bandwidth. The sixth order filter had been fabricated in the standard 0.18 ìm CMOS process using 1.8-V supply. The chip occupies only 0.9 mm 0.9 mm silicon area and has a power consumption of 130-mW. The measured center frequency was tunable from 3.54 GHz to 3.88 GHz, bandwidth was tunable from 35 MHz to 80 MHz. With a 65 MHz bandwidth, the filter had a gain of 13 dB, an IIP3 of -29 dBm and a P1dB of -46 dBm.

Les tecnologies sense fils han provocat una important revolució en el món de les xarxes i serveis de telecomunicació. Han apareguts nous sistemes com els telèfons mòbils d'última generació o les xarxes LAN sense fils que han estat acceptats amb entusiasme per la població. En particular, l'ús de xarxes de sensors (per controlar la temperatura, per a detectar places lliures d'aparcament, etc.) està creixent ràpidament . Aquesta tesi es centra en el disseny d'antenes per a xarxes de sensors distribuïts. En concret s'analitza un sistema on els sensors remots estan connectats a una unitat central utilitzant un radio enllaç operant en la banda ISM de 5,8 GHz, i la unitat central envia la informació recollida a Internet a través d'una connexió WLAN. A la unitat central es necessiten antenes multibanda per cobrir diverses bandes de freqüències amb un únic element radiant. En aquesta tesi es presenten dues solucions per obtenir aquest comportament multibanda: Monopols amb pla de massa fractal i monopols carregats amb ressonadors. S'han fabricat i mesurat diferents prototips que cobreixen les necessitats del sistema. Els sensors han de ser dispositius de reduïdes dimensions i baix cost. Una bona opció per aconseguir aquests requisits és l'ús d'antenes integrades en silici fabricades amb una tecnologia CMOS estàndard. En primer lloc s'analitzen els principals problemes de la integració de l'antena en silici, i a continuació es presenta una possible solució per millorar l'eficiència juntament amb un estudi de la degradació introduïda per altres components quan aquests es fabriquen en el mateix xip que l’antena. Les mesures dels prototips fabricats demostren que la integració de l'antena en la banda de 5,8 GHz és factible, obtenint un abast d'alguns metres. Cada vegada és una realitat més propera el fet de tenir sensors implantats en el cos. Per aquest motiu, l’última part d'aquesta tesi es dedica a estudiar els efectes del cos sobre antenes situades en el seu interior i avaluar les pèrdues de propagació addicionals introduïdes pels teixits humans. / Las tecnologías inalámbricas han provocado una importante revolución en el mundo de las redes y servicios de telecomunicación. Han aparecidos nuevos sistemas, como los teléfonos móviles de última generación o las redes LAN inalámbricas, que han sido aceptados con entusiasmo por la población. En particular, el uso de redes de sensores (para controlar la temperatura, para detectar plazas libres de aparcamiento, etc.) está creciendo rápidamente. Esta tesis se centra en el diseño de antenas para redes de sensores inalámbricos distribuidos. EN concreto se analiza un sistema donde los sensores están conectados a una unidad central utilizando un enlace inalámbrico en la banda ISM de 5.8 GHz, y la unidad central envía la información recogida a Internet a través de una conexión WLAN. En la unidad central se necesitan antenas multibanda para dar servicio a varias bandas de frecuencias con un único elemento radiante. En esta tesis se presentan dos soluciones para obtener este comportamiento multibanda: Monopolos con plano de masa fractal y monopolos cargados con resonadores. Se han fabricado y medido diferentes prototipos que cubren las necesidades del sistema. En los sensores se desean dispositivos de reducidas dimensiones y bajo coste. Una buena opción para lograr estos requisitos es el uso de antenas integradas en silicio fabricadas con una tecnología CMOS estándar. En primer lugar se analizan los principales problemas de la integración de la antena en silicio, y a continuación se presenta una posible solución para mejorar la eficiencia de radiación junto con un estudio de la degradación introducida por otros componentes cuando éstos se fabrican en el mismo chip que la antena. Las medidas de los prototipos fabricados demuestran que la integración de la antena en la banda de 5,8 GHz usando una tecnología CMOS es factible, obteniendo unos alcances de algunos metros incluso cuando la antena se fabrica junto con otros elementos integrados en el mismo chip. Cada vez es una realidad más cercana el hecho de poder tener sensores implantados en el cuerpo. Por este motivo, la última parte de esta tesis se dedica a estudiar los efectos del cuerpo sobre antenas situadas en su interior y evaluar las pérdidas de propagación adicionales introducida por los tejidos humanos. / Wireless technologies have triggered an important revolution in the world of telecommunication networks and services. New systems, such as the latest generation mobile phones or wireless LANs, have appeared being enthusiastically accepted by people. In particular, applications related to remote sensor networks are growing rapidly (for temperature monitoring, the detection of free parking spaces, etc.). This thesis is focused on antenna design for distributed wireless sensor networks. The remote sensors we are considering are connected to a central unit using a wireless link in the 5.8 GHz ISM band and the central unit transmits the collected information to the Internet via a WLAN connection. In the central unit multiband antennas are necessary to cover several frequency bands with a single radiating element. Two solutions to obtain this multiband performance are proposed: fractal-based ground planes and resonator loaded monopoles. Several novel antennas that easily meet the system requirements are manufactured and measured. For remote sensors small dimensions and low costs are desired. The use of silicon integrated antennas fabricated with standard CMOS technology is a good choice to achieve these requirements. First, the main problems of antenna integration are discussed and, then a possible solution to improve the antenna efficiency is presented together with a study of the effects of other elements integrated in the same chip with the antenna. The measurements of the manufactured prototypes demonstrate that antenna integration at 5.8 GHz is feasible, and that system ranges of some meters can be obtained even when the antenna is fabricated together with other elements integrated in the same chip. The possibility of having some of the sensors implanted inside the body will be a reality in the near future, for this reason the particular case of implanted antennas is also analyzed. The last part of this thesis is devoted to study the body effects on antenna performance and evaluate the additional propagation losses introduced by the body tissues.

During later years communication schemes for handheld devices have increased in complexity due to the desire to increase the throughput, i.e. the amount of information sent over a medium simultaneously. Increasing throughput can be accomplished, not only by modulating the phase or frequency, but also the amplitude. This leads to tougher requirements on the power amplifier. The conventional power amplifiers, which have the ability to follow the envelope of the carrier, are inefficient. This thesis aims to compare two old but revived architectures which exploit high-efficiency amplifiers and still have a linear relationship between the input and output. The architectures; the Polar Linearization Technique and Outphasing share the same foundation. Based on literature, the polar technique have been more successful of employing examples fufilling communication standards. The polar technique is also more versatile regarding power combiners, distortion correction and alternative implementations. The simulations performed in this thesis results show that the polar amplifier is less sensitive to process variations and has higher maximum efficiency. On the other hand, the outphasing topology have the highest linearity figures.

Radio frequency (RF) filters are one of the key building blocks in modern microelectronic digital communication systems that use a narrow frequency band with strong interferers nearby. The objective of this thesis is to explore the better DR performance of RF filters using the Q-enhanced LC filter. It takes a divide-and-conquer method by designing 1. A new simple pseudo-differential pair (PDP) for input gm stage. It is the fastest, high-linearity, low-distortion, and wide-range constant-gm design reported to date. This has been applied in the final filter tape-out and has proven to be effective experimentally. 2. A new tunable discrete inductor (TDL) to achieve two-level inductance with the same real estate that can be used to expand the filtering frequency range. This has been verified experimentally. 3. A new tunable discrete capacitor (TDC) to achieve high linearity over wide terminal voltage swing range. This has been verified through simulation. 4. A new systematic way to achieve synchronized gain, center frequency, and filtering Q tuning capability for Q-enhanced LC filters. It has been verified through simulation. In order to verify the concept, a 900 MHz filter is designed and fabricated with National Semiconductor Company (NSC)'s standard 0.18 um digital epi-substrate CMOS technology, and packaged with NSC's LLP-28. The measurement results show that with filter Q of 17 at 845 MHz, the 1 dB compression point is measured to be +4 dBm, IIP3 to be +16 dBm with a peak noise floor of -154 dB/Hz, spurious free dynamic range (SFDR) to be 71 dB. With filter Q of 70 over a 20 MHz BW, the 1 dB compression point is measured to be -9.5 dBm, IIP3 to be +7 dBm with a peak noise floor of -141 dB/Hz, SFDR to be 57 over 20 MHz BW. This filter uses between 56 and 60 mA with a power supply of 1.8 V due to the low-Q (Q~1) of inductor. It is the RF filter with the highest DR in the published literature. The DR can be even higher if inductor Q can be improved as DR is proportional to Q^2.

High-speed, medium-resolution, analog-to-digital converters (ADCs) are important building blocks in a wide range of applications. High-speed, medium-resolution ADCs have been implemented by various ADC architectures such as a folding ADC, a subranging ADC, and a pipeline ADC. Among them, pipeline ADCs have proven to be efficient architectures for applications such as digital communication systems, data acquisition systems and video systems. Especially, power dissipation is a primary concern in applications requiring portability. Thus, the objective of this work is to design and build a low-voltage low-power medium-resolution (8-10bits) high-speed pipeline ADC in deep sub-micron CMOS technology. The non-idealities of the circuit realization are carefully investigated in order to identify the circuit requirements for a low power circuit design of a pipeline ADC. The resolution per stage plays an important role in determining overall power dissipation of a pipeline ADC. The pros and cons of both large and small number of bits per-stage are examined. A power optimization algorithm is developed to decide more accurately which approach is better for lower power dissipation. Both identical and non-identical number of bit per-stage approaches are considered and their differences are analyzed. A low-power, low-voltage 10-bit 100Msamples/s pipeline ADC was designed and implemented in a 0.18mm CMOS process. The power consumption was minimized with the right selection of the per-stage resolution based on the result of the power optimization algorithm and by the scaling down the sampling capacitor size in subsequent stages.

IEEE 802.15 High Rate Alternative PHY task group (TG3a) is working to define a protocol for Wireless Personal Area Networks (WPANs) which makes it possible to attain data rates of greater than 110Mbps. Ultra Wideband (UWB) technology utilizing frequency band of 3.168 GHz – 10.6 GHz is an emerging solution to this with data rates of 110, 200 and 480 Mbps. Initially, UWB mode I devices using only 3.168 GHz – 4.752 GHz have been proposed. Low Noise Amplifier (LNA) and I-Q mixers are key components constituting the RF front-end. Performance of these blocks is very critical to the overall performance of the receiver. In general, main considerations for the LNA are low noise, 50 broadband input matching, high gain with maximum flatness and good linearity. For the mixers, it is essential to attain low flicker noise performance coupled with good conversion gain. Proposed LNA architecture is a derivative of inductive source degenerated topology. Broadband matching at the LNA output is achieved using LC band-pass filter. To obtain high gain with maximum flatness, an LC band-pass filter is used at its output. Proposed LNA achieved a gain of 15dB, noise figure of less than 2.6dB and IIP3 of more than -7dBm. Mixer is a modified version of double balanced Gilbert cell topology where both I and Q channel mixers are merged together. Frequency response of each sub-band is matched by using an additional inductor, which further improves the noise figure and conversion gain. Current bleeding scheme is used to further reduce the low frequency noise. Mixer achieves average conversion gain of 14.5dB, IIP3 more than 6dBm and Double Side Band (DSB) noise figure less than 9dB. Maximum variation in conversion gain is desired to be less than 1dB. Both LNA and mixers are designed to be fabricated in TSMC 0.18µm CMOS technology.

With the increasing demand for high quality TV service, digital television (DTV) is replacing the conventional analog television. DTV tuner is one of the most critical blocks of the DTV receiver system; it down-converts the desired DTV RF channel to baseband or a low intermediate frequency with enough quality. This research is mainly focused on the analysis and realization of low-cost low-power front-ends for ATSC terrestrial DTV and DVB-H mobile DTV tuner systems. For the design of the ATSC terrestrial tuner, a novel double quadrature tuner architecture, which can not only minimize the tuner power consumption but also achieve the fully integration, has been proposed. A double quadrature down-converter has been designed and fabricated with TSMC 0.35µm CMOS technology; the measurement results verified the proposed concepts. For the mobile DTV tuner, a zero-IF architecture is used and it can achieve the DVB-H specifications with less than 200mW power consumption. In the implementation of the mobile DVB-H tuner, a novel RF variable gain amplifier (RFVGA) and a low flicker noise current-mode passive mixer have been proposed. The proposed RFVGA achieves high dynamic range and robust input impedance matching performance, which is the main design challenge for the traditional implementations. The current-mode passive mixer achieves high-gain, low noise (especially low flicker noise) and high-linearity (over 10dBm IIP3) with low power supplies; it is believed that this is a promising topology for low voltage high dynamic range mixer applications. The RFVGA has been fabricated in TSMC 0.18µm CMOS technology and the measurement results agree well with the theoretical ones.

For many decades silicon based CMOS technology has made continual increase in drive current to achieve higher speed and lower power by scaling the gate length and the gate insulator thickness. The scaling becomes increasingly challenging because the devices are approaching physical quantum limits. Three-dimensional electronic devices, such as double gate, tri-gate and nanowire field-effect-transistors (FETs) provide an alternative solution because the ultra-thin fin or nanowire provides better electrostatic control of the device channel. Also high-[kappa] oxides lower the gate leakage current significantly, due to larger thickness for the same equivalent oxide thickness (EOT) compared with SiO₂ beyond the 22 nm node. Moreover, metal gate that avoids the poly-depletion effect in poly-Si gate has become mainstream semiconductor technology. The enabler technologies for high-[kappa] / metal gate 3D transistors include fabrication of high quality, vertical nanowire arrays, conformal metal and dielectric deposition and vertical patterning. One of the main focuses of this dissertation is developing a fabrication process flow to realize high performance MOSFETs with high-[kappa] oxide and metal gate on vertical silicon nanowire arrays. A variety of approaches to fabricating highly ordered silicon nanowire arrays have been achieved. Deep silicon etching process was developed and optimized for nanowire FETs. Process integration and patterning mythologies for high-[kappa] / metal gate were investigated and accomplished. 3-D electronic devices including nanowire capacitors, nanowire FETs and double gate MOSFETs for power applications were fabricated and characterized. The second part of this dissertation is about flexible electronics. Mechanically flexible integrated circuits (ICs) have gained increasing attention in recent years with emerging markets in portable electronics. Although a number of thin-film-transistor (TFT) IC solutions have been reported, challenges still remain for fabrication of inexpensive, high performance flexible devices. We report a simple and straightforward solution: mechanically exfoliating a thin Si film containing ICs. Transistors and circuits can be pre-fabricated on bulk silicon wafer with conventional CMOS process flow without additional temperature or process limitations. The short channel MOSFETs exhibit similar electrical performance before and after exfoliation. This exfoliation process also provides a fast and economical approach to produce thinned silicon wafers, which is a key enabler for three-dimensional (3D) silicon integration based on Through Silicon Vias (TSVs). / text

Since metal-oxide-semiconductor (MOS) device was first reported around 1959 and utilized for integrated circuits in 1961, complementary MOS technology has become the mainstream of semiconductor industry. Its performance has been improved based on scaling of dimensions of MOS field-effect-transistors (MOSFET) in accordance with Moore’s law, which states that the density of MOSFETs due to scaling approximately doubles every two years. Entering into sub-100nm regime caused a lot of challenges. Traditional way of scaling no longer provided performance enhancement of individual MOSFETs. Increased channel doping which is required to prevent degradation of device electrostatics from short channel effects caused carrier mobility degradation. New inventions needed to be incorporated to sustain performance enhancement trend with scaling. Implementation of process induced strained Si technology allowed mobility enhancement, and high-K/metal gate instead of conventional poly-Si/SiO2 allowed continuing electrical gate oxide thickness scaling, hence extending the life span of Moore’s law. As we are now moving toward 22nm logic technology and below, new concerns have been rapidly aroused. Controlling power consumption and performance variability are becoming as important as developing scaled devices with enhanced performance. Expandability of strained-Si channel technology via process induced strain also faces increasing complexity from ever tighter gate pitch and difficulties in controlling defect level with the channel stress enhancement techniques. At the same time, long-lasting planar MOSFET architecture also faces serious challenges due to the limits of controlling short channel effects. New paradigms and pathways for future technology seems to be required. As a result, new material sets, new device architectures and concepts are being vigorously explored in the literature. These new trends can be categorized into three groups: MOSFET structure with (non-Si) high mobility channel materials, advanced (non-planar) MOSFET structures, and MOSFET-type structures with new device operation concepts such as tunneling FETs. This dissertation presents research on high mobility channel MOSFET structures (planar and non-planar) using group IV material (mainly SiGe) for enhanced performance and reduced operating power. This work especially focuses on improving the performance of short channel device performance of SiGe channel pMOSFETs which has long been researched yet clearly demonstrated in literature only recently. To reach the goal, novel processing technologies such as millisecond flash source/drain anneal and high pressure hydrogen post-metal anneal are explored. Finally, performance dependence on channel and substrate direction has been analyzed to find the optimal use of these SiGe channels. This work describes an exciting opportunity of weighting the possibility of using high mobility channel MOSFETs for future logic technology. / text

This thesis focuses on the design of radio-frequency (RF) mixers, including a broadband downconverter mixer, an upconverter mixer and a downconverter mixer with high linearity. The basic mixer topology used in this thesis was the Gilbert cell mixer, which is the most popular mixer topology in modern communication systems. In order to accommodate different applications, the broadband mixer and the upconverter mixer were designed to be reconfigurable. First, a broadband downconverter mixer with variable conversion gain was designed using 0.13-$\mu m$ CMOS technology. The mixer worked from 2 to 10 GHz. By changing the effective transistor size of the transconductor and the load, the mixer was able to work in three different modes with different conversion gain and power consumption. Second, an upconverter mixer with sideband selection was demonstrated in CMOS 0.13-$\mu$m technology. The transmitted sideband could be chosen to be the upper sideband or the lower sideband. The mixer worked at 5 GHz with a 100 MHz IF. The measured voltage conversion gains were 11.2 dB at 4.9 GHz and 12.4 dB at 5.1 GHz. The best sideband rejection was around 30 dB. Third, a modified derivative superposition (DS) technique was used to linearize a Gilbert cell mixer. Simulation results predicted an IIP3 improvement of 12.5 dB at 1 GHz. After linearization, the noise figure of the mixer increased by only 0.7 dB and the conversion gain decreased by 0.3 dB. The power consumption of the mixer increased by 0.96 mW. / Thesis (Master, Electrical & Computer Engineering) -- Queen's University, 2010-06-18 14:40:35.062