Double cantilever beam (DCB) specimens with distinct intermetallic microstructures and different geometries were fractured under different mode ratios of loading, ψ, to obtain critical strain energy release rate, Jc. The strain energy release rate at crack initiation, Jci, increased with phase angle, ψ, but remained unaffected by the joint geometry. However, the steady-state energy release rate, Jcs, increased with the solder layer thickness. Also, both the Jci and Jcs decreased with the thickness of the intermetallic compound layer. Next, mode I and mixed-mode fracture tests were performed on discrete (l=2 mm and l=5 mm) solder joints arranged in a linear array between two copper bars to evaluate the J = Jci (ψ) failure criteria using finite element analysis. Failure loads of both the discrete joints and the joints in commercial electronic assemblies were predicted reasonably well using the Jci from the continuous DCBs. In addition, the mode-I fracture of the discrete joints was simulated with a cohesive zone model which predicted reasonably well not only the fracture loads but also the overall load-displacement behavior of the specimen. Additionally, the Jci calculated from FEA were verified estimated from measured crack opening displacements in both the continuous and discrete joints. Finally, the pad-crater fracture mode of solder joints was characterized in terms of the Jci measured at various mode ratios, ψ. Specimens were prepared from lead-free chip scale package-PCB assemblies and fractured at low and high loading rates in various bending configurations to generate a range of mode ratios. The specimens tested at low loading rates all failed by pad cratering, while the ones tested at higher loading rates fractured in the brittle intermetallic layer of the solder. The Jci of pad cratering increased with the phase angle, ψ, but was independent of surface finish and reflow profile. The generality of the J =Jci(ψ) failure criterion to predict pad cratering fracture was then demonstrated by predicting the fracture loads of single lap-shear specimens made from the same assemblies.

Double cantilever beam (DCB) specimens with distinct intermetallic microstructures and different geometries were fractured under different mode ratios of loading, ψ, to obtain critical strain energy release rate, Jc. The strain energy release rate at crack initiation, Jci, increased with phase angle, ψ, but remained unaffected by the joint geometry. However, the steady-state energy release rate, Jcs, increased with the solder layer thickness. Also, both the Jci and Jcs decreased with the thickness of the intermetallic compound layer. Next, mode I and mixed-mode fracture tests were performed on discrete (l=2 mm and l=5 mm) solder joints arranged in a linear array between two copper bars to evaluate the J = Jci (ψ) failure criteria using finite element analysis. Failure loads of both the discrete joints and the joints in commercial electronic assemblies were predicted reasonably well using the Jci from the continuous DCBs. In addition, the mode-I fracture of the discrete joints was simulated with a cohesive zone model which predicted reasonably well not only the fracture loads but also the overall load-displacement behavior of the specimen. Additionally, the Jci calculated from FEA were verified estimated from measured crack opening displacements in both the continuous and discrete joints. Finally, the pad-crater fracture mode of solder joints was characterized in terms of the Jci measured at various mode ratios, ψ. Specimens were prepared from lead-free chip scale package-PCB assemblies and fractured at low and high loading rates in various bending configurations to generate a range of mode ratios. The specimens tested at low loading rates all failed by pad cratering, while the ones tested at higher loading rates fractured in the brittle intermetallic layer of the solder. The Jci of pad cratering increased with the phase angle, ψ, but was independent of surface finish and reflow profile. The generality of the J =Jci(ψ) failure criterion to predict pad cratering fracture was then demonstrated by predicting the fracture loads of single lap-shear specimens made from the same assemblies.

The phenomena studied in Fracture Mechanics can be observed either in Nature, the most sophisticated systems or ordinary structures. As a consequence, Engineers need to be alert for investigating the variety of complex mechanisms, related with fracture processes, which are capable of appearing in these systems. The possibility of failure is a real premise has to be considered not only in the design of structures, but also throughout their life. Undoubtedly, in this context Fracture Mechanics should be used to carry out prognostics of potential crack propagation patterns, verifying if there exists or not risk of keeping a structure in service usage. An alternative formulation widely applied to simulate fracture behavior is the Cohesive Zone Modeling (CZM) approach. It is a scientific branch of Fracture Mechanics originally proposed by Barenblatt (1959, 1962) and Dugdale (1960), and which after Xu and Needleman s works (1993, 1994) has acquired a great acceptance in scientific community. For this reason, the present work employs Xu and Needleman s model to simulate dynamic crack propagation in brittle materials, introducing the Software for Simulation of Dynamic Cohesive Fracture (DyCOH), which is based on Object-Oriented Programming (OOP) paradigm for facilitating future reuse and extension of implemented code. Using DyCOH software two numerical applications are shown. First, for verification purpose, the classical Xu and Needleman s problem is simulated and the response of DyCOH is compared with literature results. Second, for didactic aspiration, a simpler problem is studied in order to understand the influence of loading speed on fracture patterns of a tie-bar. / Coordenação de Aperfeiçoamento de Pessoal de Nível Superior / Os fenômenos estudados pela Mecânica da Fratura podem ser observados na própria Natureza, em sistemas de altíssimo padrão tecnológico, bem como em estruturas mais tradicionais. Dessa forma, os engenheiros devem estar alerta para investigar a variedade de mecanismos complexos, relacionados aos processos de fratura, que podem surgir nesses sistemas. Nesse sentido, a possibilidade de falha precisa ser encarada como uma premissa real a ser observada não somente nas etapas de projeto, mas durante toda vida útil das estruturas. Sem dúvida, para auxiliar nessa tarefa, a Mecânica da Fratura pode ser utilizada através da realização de prognósticos dos potenciais padrões de propagação de trincas, verificando a existência ou não de risco de manter determinada estrutura em serviço. Uma formulação alternativa que vem sendo amplamente empregada para a simulação do comportamento a fratura é a de Modelos de Zona Coesiva. Estes formam um ramo da Mecânica da Fratura originalmente proposto por Barenbllat (1959, 1962) e Dugdale (1960), e que depois dos trabalhos de Xu e Needleman (1993, 1994) tem recebido uma grande aceitação no meio científico. Assim sendo, o presente trabalho emprega o modelo coesivo de Xu e Needleman para simulação da propagação dinâmica de fraturas em matérias frágeis, dando início a construção do DyCOH (Software for Simulation of Dynamic Cohesive Fracture ). Este é concebido com base nos conceitos de programação orientada a objetos, visando facilitar o reuso e a extensibilidade do código base. Através do DyCOH, duas aplicações numéricas são realizadas. Na primeira, o problema clássico de Xu e Needleman é simulado e os resultados obtidos pelo DyCOH são comparados com os disponíveis na literatura técnica, de forma a realizar a verificação numérica do código. No segundo, um problema mais simples é estudado com objetivo de entender a influência da velocidade de aplicação do carregamento no padrão de fraturamento de um tirante, permitindo observar a capacidade do DyCOH em reproduzir um exemplo mais didático.

With continued feature size reduction in microelectronics and with more than a billion transistors on a single integrated circuit (IC), on-chip interconnection has become a challenge in terms of processing-, electrical-, thermal-, and mechanical perspective. Today’s high-performance ICs have on-chip back-end-of-line (BEOL) layers that consist of copper traces and vias interspersed with low-k dielectric materials. These layers have thicknesses in the range of 100 nm near the transistors and 1000 nm away from the transistors close to the solder bumps. In such BEOL layered stacks, cracking and/or delamination is a common failure mode due to the low mechanical and adhesive strength of the dielectric materials as well as due to high thermally-induced stresses. However, there are no available cohesive zone models and parameters to study such interfacial cracks in sub-micron thick microelectronic layers. This work focuses on developing framework based on cohesive zone modeling approach to study interfacial delamination in sub-micron thick layers. Such a framework is then successfully applied to predict microelectronic device reliability. As intentionally creating pre-fabricated cracks in such interfaces is difficult, this work examines a combination of four-point bend and double-cantilever beam tests to create initial cracks and to develop cohesive zone parameters over a range of mode-mixity. Similarly, a combination of four-point bend and end-notch flexure tests is used to cover additional range of mode-mixity. In these tests, silicon wafers obtained from wafer foundry are used for experimental characterization. The developed parameters are then used in actual microelectronic device to predict the onset and propagation of crack, and the results from such predictions are successfully validated with experimental data. In addition, nanoindenter-based shear test technique designed specifically for this study is demonstrated. The new test technique can address different mode mixities compared to the other interfacial fracture characterization tests, is sensitive to capture the change in fracture parameter due to changes in local trace pattern variations around the vicinity of bump and the test mimics the forces experienced by the bump during flip-chip assembly reflow process. Through this experimental and theoretical modeling research, guidelines are also developed for the reliable design of BEOL stacks for current and next-generation microelectronic devices.