Advancements in the sophistication and complexity of modern electronic systems are creating a need for highly integrated systems with ever higher operational frequencies. The economical demands of these systems dictate that they be implemented using low cost fabrication technologies, such as digital CMOS. One of the major challenges facing circuit designers is the difficulty in implementing high frequency RF analog circuits on these types of technologies. Analog circuits which make use of parasitic-laden components such as inductors are especially difficult to realize. The purpose of this thesis is to investigate the design and application of an optimization tool based on simulated annealing to this type of problem. The goal is to have the optimizer incorporate these unavoidable component parasitics into a design, and thus eliminate any undesirable performance degradation. The optimization technique will be applied to the design of a CMOS RF distributed amplifier. This type of amplifier has a flat gain characteristic over an exceptionally wide bandwidth, and it is heavily reliant on inductive structures. Historically, an amplifier of this type has never been implemented on a standard CMOS process, without the use of bondwire inductances or special processing techniques. However, it will be shown in this thesis that, with the aid of the optimization technique, a distributed amplifier design can be successfully realized on a standard CMOS process. / Graduation date: 1999

Currently, the two most critical factors of microprocessor design are performance and power. The optimum balance of these two factors is reflected in the speed-power product(SPP). 32-bit CMOS adders are used as representative circuits to investigate a method of reducing the SPP. The purpose of this thesis is to show that sizing gates according to fan-out and removing buffer drivers can reduce the SPP. This thesis presents a method for sizing gates in large fan-out parallel prefix circuits to reduce the SPP and compares it to other methods. Three different parallel prefix adders are used to compare propagation delay and SPP. The first adder uses the depth-optimal prefix circuit. The second adder is based on Wei, Thompson, and Chen's time-optimal adder. The third adder uses a recursive doubling formation where all cells have minimum transistor width dimensions. The component cells in the adders are static CMOS as described by Brent and Kung. For all circuits, the smallest propagation delay occurs when the highest voltage supply is applied. The smallest SPP occurs when the lowest voltage supply is applied, but with the lowest performance. The Recursive Doubling Adder always has the lowest propagation delay for a particular set of parameters. However, its SPP is nearly equal to the Brent-Kung Adders and lower than Wei's Adder. The power-frequency analysis reveals that a decrease in Vt causes higher power consumption due to leakage. / Graduation date: 1999

In this thesis, novel design techniques have been proposed for implementing high-linearity SC circuits in a standard digital CMOS process. They use nonlinear MOSFET capacitors instead of linear double-poly capacitors. To reduce their nonlinearities, a bias voltage is applied to keep MOSFET capacitors in their accumulation regions. For further reduction of distortion, two capacitors can be connected in series or in parallel so that a first-order cancellation of the nonlinearity can be achieved. Experimental results demonstrated that the among these techniques series compensation is the most effective for reducing the nonlinearity of MOSFET capacitors. A novel predictive SC amplifier has been proposed for its insensitivity to op-amp imperfections. Experimental results show that the S/THD of the predictive SC amplifier was 10 dB larger than that of the non-predictive one. It was also shown that a predictive circuit was effective for reducing the nonlinearity caused by the op-amp and/or the MOSFET capacitors. It has been demonstrated that a two-stage op-amp with a large output swing can be fabricated in a standard digital CMOS process. The frequency compensation was accomplished using a source follower and a MOSFET capacitor. An SC amplifier using this two-stage op-amp and double-poly capacitors was fabricated, and it exhibited a large linear output range. A MOSFET-only digitally controlled gain/loss circuit was designed and fabricated in a 1.2�� CMOS process. It demonstrated that the series compensation is effective not only for a large output swing in an amplifier, but also for a large input swing in an attenuator. A pipeline D/A converter utilizing MOSFET capacitors was designed as another application of charge processing technique. It consisted of three parts: a V-Q conversion stage, a charge transfer stage, and a Q-V converter. A new switch configuration which enables the series compensation to have a large bias voltage has also been proposed. It was shown that it works well, and it will be helpful for low-voltage operation, too. / Graduation date: 1998

Substrate switching noise is becoming a concern as integrated circuits get larger and speeds get faster. Mixed-mode integrated circuits are especially affected as the substrate noise interferes with sensitive analog circuits resulting in limited signal to noise ratios. This thesis serves to study the cause of the noise at the point where it is generated to the way it propagates to the analog circuits, and presents several approaches to reduce the switching noise. In addition, it examines the substrate impedance as being a key element to successful and reliable design for low-noise CMOS mixed-signal integrated circuits. Utilizing the substrate lead inductance and current-variable capacitances through the use of guard ring diodes, resonant frequencies which provide a low impedance path to ground are created. These can be tuned to coincide with problematic noise frequency components or to cancel the pin and package resonance, thus suppressing noise and improving reliability. / Graduation date: 1997

A CMOS implementation of a True-Q Flip Flop is presented. It can perform either as an asynchronous storage element in micropipelines or a part of the synchronizer. It is capable of double-edge triggering which latches data at both the rising and the trailing edges. It is also free of the metastability state problem. Some analog and digital circuits are incorporated with a true double-edge triggered Flip Flop (DETFF) making it a True-Q Flip Flop. A True-Q Flip Flop outputs an acknowledge signal only after the Q and NQ are stabilized. Therefore, if the proceeding stages utilize this acknowledge signal as the triggering signal, then, the value of Q from the flip flop will not be received by the next stage if Q is in a metastable state. The number of transistors used in this implementation of True-Q flip flop is 90. Due to the overhead of circuit complexity, the time delay from Request to Acknowledge signal is 6.5ns. / Graduation date: 1995

Graduation date: 1994

Not available

Thesis (Ph.D.)--Hong Kong University of Science and Technology, 2007. / Includes bibliographical references (leaves 135-145). Also available in electronic version.

Thesis (Ph.D.)--Ohio University, June, 2006. / Title from PDF t.p. Includes bibliographical references (p. [69]-[78])

Illamående och kräkning är förekommande biverkningar hos patienter med cancer som behandlas med cytostatika och är därmed tillstånd som sjuksköterskan kommer i kontakt med. Om patientens illamående och kräkning inte förebyggs kan det leda till konsekvenser som att patienten blir dehydrerad, tappar aptiten, blir undernärd och försvårar skadad vävnad att återhämta sig från cytostatikabehandling. Trots att de flesta patienter får antiemetika lyckas inte deras illamående och kräkning förebyggas. Syftet var att belysa komplementära behandlingsmetoder vid cytostatikarelaterat illamående och kräkning. Studien är utförd som en litteraturstudie och baserad på 14 vetenskapliga studier. Resultatet visar att komplementära behandlingsmetoder har ett visst vetenskapligt stöd och är ett bra komplement till antiemetika. Akupressur är den behandlingsmetod som är effektivast för att förebygga cytostatikarelaterat illamående och kräkning. Även akustimulation, elektroakupunktur och avslappning minskar patienternas illamående och kräkning. Mer forskning behövs för att ge mer styrka åt de olika komplementära behandlingsmetoder, eftersom sjuksköterskans arbete måste utföras utifrån vetenskap och beprövad erfarenhet. Genom att sjuksköterskan får ökad kunskap om hur cytostatikarelaterat illamående och kräkning förebyggs kan patientens lidande minska.