Technology trends such as growing wire delays, power consumption limits, and diminishing clock rate improvements, present conventional instruction set architectures such as RISC, CISC, and VLIW with difficult challenges. To show continued performance growth, future microprocessors must exploit concurrency power efficiently. An important question for any future system is the division of responsibilities between programmer, compiler, and hardware to discover and exploit concurrency. In this research we develop the first compiler for an Explicit Data Graph Execution (EDGE) architecture and show how to solve the new challenge of compiling to a block-based architecture. In EDGE architectures, the compiler is responsible for partitioning the program into a sequence of structured blocks that logically execute atomically. The EDGE ISA defines the structure of, and the restrictions on, these blocks. The TRIPS prototype processor is an EDGE architecture that employs four restrictions on blocks intended to strike a balance between software and hardware complexity. They are: (1) fixed block sizes (maximum of 128 instructions), (2) restricted number of loads and stores (no more than 32 may issue per block), (3) restricted register accesses (no more than eight reads and eight writes to each of four banks per block), and (4) constant number of block outputs (each block must always generate a constant number of register writes and stores, plus exactly one branch). The challenges addressed in this thesis are twofold. First, we develop the algorithms and internal representations necessary to support the new structural constraints imposed by the block-based EDGE execution model. This first step provides correct execution and demonstrates the feasibility of EDGE compilers. Next, we show how to optimize blocks using a dataflow predication model and provide results showing how the compiler is meeting this challenge on the SPEC2000 benchmarks. Using basic blocks as the baseline performance, we show that optimizations utilizing the dataflow predication model achieve up to 64% speedup on SPEC2000 with an average speedup of 31%. / text

No description available.

No description available.

The dissertation is a description of an analysis and a case study of an Optimization Stage for a Standard Cell oriented silicon compiler. Using the AHPL hardware description language, a complete representation hierarchy (functional, logic, and layout) is proposed for circuits defined at a Register Transfer level. The design of a new class of methods for layout analysis and optimization is based on this hierarchy. A layout evaluation method is based on the analysis of an activity graph derived from a circuit layout. The cost measure for such a graph is defined and used in evaluation of the necessary and sufficient conditions for design optimality (NSCDO). Iterations within the optimization process are controlled using a synthetic measure derived from these optimality conditions. A proposed layout optimization heuristic, derived from NSCDO, allows for better routing channel area utilization without compromising a circuit's timing performance. It is based on an analysis of the timing behavior modifications introduced by the various materials used as interconnectors resulting in an improvement of the load dependency of the output driving capabilities of cells. The dissertation contains an example of a quantitative analysis of a CMOS digital circuit. A system implementing some of the algorithms described above has been written in FORTRAN77.

No description available.

No description available.

No description available.

No description available.

No description available.

No description available.