Thesis (Ph. D.)--University of Texas at Austin, 2007. / Vita. Includes bibliographical references.

Thesis (D.Eng.)--University of Delaware, 2007. / Principal faculty advisor: Guang R. Gao, Dept. of Electrical and Computer Engineering. Includes bibliographical references.

Thesis (M. Sc.)--University of Canterbury, 2007. / Typescript (photocopy). Includes bibliographical references (p. 149-159). Also available via the World Wide Web.

Thesis (M.S.)--Mississippi State University. Department of Electrical and Computer Engineering. / Title from title screen. Includes bibliographical references.

Thesis (Ph. D.)--University of Texas at Austin, 2008. / Vita. Includes bibliographical references.

Στη σύγχρονη εποχή το κενό απόδοσης μεταξύ του επεξεργαστή και της μνήμης ενός σύγχρονου υπολογιστικού συστήματος συνεχώς μεγαλώνει. Είναι λοιπόν σημαντικό να ερευνηθούν νέοι τρόποι για να καλυφθεί η αδυναμία της κύριας μνήμης να ακολουθήσει τον επεξεργαστή. Η μνήμη cache ήταν ανέκαθεν ένα χρήσιμο εργαλείο προς αυτήν την κατεύθυνση. Χρειάζεται όμως πλέον να προχωρήσει πέρα από την απλοϊκή μορφή της και τον αλγόριθμο LRU Η παρούσα διπλωματική έχει σαν σκοπό την μελέτη της cache σε πραγματικό περιβάλλον και την ανάλυση της δυνατότητας και της χρησιμότητας της πρόβλεψης της συμπεριφοράς ενός σύγχρονου προγράμματος όσον αφορά την προσπέλαση της μνήμης. Η εργασία επικεντρώνεται στην χρήση τεχνικών dynamic instrumentation για την υλοποίηση ενός μηχανισμού πρόβλεψης της απόστασης επαναχρησιμοποίησης μιας θέσης μνήμης, μέσω της ανάλυσης και μελέτης της συμπεριφοράς της εντολής, που ζητά να προσπελάσει την συγκεκριμένη θέση μνήμης. Αναλύεται εκτενώς η λειτουργία ενός τέτοιου μηχανισμού και παρέχονται στατιστικές μετρήσεις που επιβεβαιώνουν την χρησιμότητα και ευστοχία μιας τέτοιας πρόβλεψης. / In contemporary times the performance gap between the CPU and the main memory of a modern computer system grows larger. So it is important to find new ways to cover the inability of the main memory to cope with the CPU’s performance. Cache memory has always been a useful tool towards this goal. However the need arises for it to move beyond simplistic implementations and algorithms like LRU. The present end year project aims towards the study of cache memory in a real time environment and the analysis of the capability and usefulness of prediction of the memory access behaviour of a modern program. The thesis puts weight on the use of dynamic instrumentation techniques for the creation of a prediction mechanism of the reuse distance of a memory address, through the analysis and study of the behavior of the instruction that accessed this memory address. The function of such a mechanism is analyzed in depth and statistical measures are provided to prove the usefulness and accuracy of such a prediction.

- / -

A new control flow model called flow grammars is introduced which unifies the treatment of intraprocedural and interprocedural control flow. This model provides excellent support for the rapid prototyping of flow analyzers. Flow grammars are an easily understood, easily constructed and flexible representation of control flow, forming an effective bridge between the usual control flow graph model of traditional compilers and the continuation passing style of denotational semantics. A flow grammar semantics is given which is shown to summarize the effects all possible executions generated by a flow grammar conservatively. Various interpretations of flow grammars for data flow analysis are explored, including a novel bidirectional interprocedural variant. Several algorithms, based on a similar technique called grammar flow analysis, for solving the equations arising from the interpretations are given. Flow grammars were developed as a basis for FACT (Flow Analysis Compiler Tool), a compiler construction tool for the automatic construction of flow analyzers. Several important analyses from the literature are cast in the flow grammar framework and their implementation in a FACT prototype is discussed. / Graduate

abstract: In this thesis I introduce a new direction to computing using nonlinear chaotic dynamics. The main idea is rich dynamics of a chaotic system enables us to (1) build better computers that have a flexible instruction set, and (2) carry out computation that conventional computers are not good at it. Here I start from the theory, explaining how one can build a computing logic block using a chaotic system, and then I introduce a new theoretical analysis for chaos computing. Specifically, I demonstrate how unstable periodic orbits and a model based on them explains and predicts how and how well a chaotic system can do computation. Furthermore, since unstable periodic orbits and their stability measures in terms of eigenvalues are extractable from experimental times series, I develop a time series technique for modeling and predicting chaos computing from a given time series of a chaotic system. After building a theoretical framework for chaos computing I proceed to architecture of these chaos-computing blocks to build a sophisticated computing system out of them. I describe how one can arrange and organize these chaos-based blocks to build a computer. I propose a brand new computer architecture using chaos computing, which shifts the limits of conventional computers by introducing flexible instruction set. Our new chaos based computer has a flexible instruction set, meaning that the user can load its desired instruction set to the computer to reconfigure the computer to be an implementation for the desired instruction set. Apart from direct application of chaos theory in generic computation, the application of chaos theory to speech processing is explained and a novel application for chaos theory in speech coding and synthesizing is introduced. More specifically it is demonstrated how a chaotic system can model the natural turbulent flow of the air in the human speech production system and how chaotic orbits can be used to excite a vocal tract model. Also as another approach to build computing system based on nonlinear system, the idea of Logical Stochastic Resonance is studied and adapted to an autoregulatory gene network in the bacteriophage λ. / Dissertation/Thesis / Ph.D. Electrical Engineering 2011

abstract: Thanks to continuous technology scaling, intelligent, fast and smaller digital systems are now available at affordable costs. As a result, digital systems have found use in a wide range of application areas that were not even imagined before, including medical (e.g., MRI, remote or post-operative monitoring devices, etc.), automotive (e.g., adaptive cruise control, anti-lock brakes, etc.), security systems (e.g., residential security gateways, surveillance devices, etc.), and in- and out-of-body sensing (e.g., capsule swallowed by patients measuring digestive system pH, heart monitors, etc.). Such computing systems, which are completely embedded within the application, are called embedded systems, as opposed to general purpose computing systems. In the design of such embedded systems, power consumption and reliability are indispensable system requirements. In battery operated portable devices, the battery is the single largest factor contributing to device cost, weight, recharging time, frequency and ultimately its usability. For example, in the Apple iPhone 4 smart-phone, the battery is $40\%$ of the device weight, occupies $36\%$ of its volume and allows only $7$ hours (over 3G) of talk time. As embedded systems find use in a range of sensitive applications, from bio-medical applications to safety and security systems, the reliability of the computations performed becomes a crucial factor. At our current technology-node, portable embedded systems are prone to expect failures due to soft errors at the rate of once-per-year; but with aggressive technology scaling, the rate is predicted to increase exponentially to once-per-hour. Over the years, researchers have been successful in developing techniques, implemented at different layers of the design-spectrum, to improve system power efficiency and reliability. Among the layers of design abstraction, I observe that the interface between the compiler and processor micro-architecture possesses a unique potential for efficient design optimizations. A compiler designer is able to observe and analyze the application software at a finer granularity; while the processor architect analyzes the system output (power, performance, etc.) for each executed instruction. At the compiler micro-architecture interface, if the system knowledge at the two design layers can be integrated, design optimizations at the two layers can be modified to efficiently utilize available resources and thereby achieve appreciable system-level benefits. To this effect, the thesis statement is that, ``by merging system design information at the compiler and micro-architecture design layers, smart compilers can be developed, that achieve reliable and power-efficient embedded computing through: i) Pure compiler techniques, ii) Hybrid compiler micro-architecture techniques, and iii) Compiler-aware architectures''. In this dissertation demonstrates, through contributions in each of the three compiler-based techniques, the effectiveness of smart compilers in achieving power-efficiency and reliability in embedded systems. / Dissertation/Thesis / Ph.D. Computer Science 2012