Thesis. 1978. M.S.--Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science. / MICROFICHE COPY AVAILABLE IN ARCHIVES AND ENGINEERING. / Bibliography: leaves 166-175. / M.S.

A new heuristic method to improve the I/O pad assignment for the sea-of-gates placement algorithm "PROUD" is proposed. In PROUD, the preplaced I/O pads are used as the boundary conditions in solving sparse linear equations to obtain the optimal module placement. Due to the total wire length determined by the module positions is the strong function of the preplaced I/O pad positions, the optimization of the I/O pad circular order and their assignment to the physical locations on the chip are attempted in the thesis. The proposed I/O pad assignment program is used as a predecessor of PROUD. The results have revealed excellent improvement.

Bibliography: p. 199-207. Electronic publication; full text available in PDF format; abstract in HTML format. Describes the basis of a theoretical and experimental project, directed at the design and evaluation of a practical active noise control system suitable for a single light engine aircraft. The performance of virtual sensors were evaluated both analytically and experimentally in progressively more complex environments to identify their capabilities and limitations. Electronic reproduction.[Australia] :Australian Digital Theses Program,2001.

The document describes the development of a micro-processor based terminal multiplexer to connect four terminals to a standard Hewlett Packard series 1000 mini-computer. The project was required to fulfill the dual roll of both increasing the number of terminals that the HPI000 could support and of reducing the peripheral load on the host CPU. The final product occupied a standard 200mm square HP size interface card and used an 8085 micro-processor and several 8085 family peripheral chips to provide four full duplex serial channels and a high speed data link with the host. A multi-tasking executive was written to control the multiplexer software which was finally implemented as 15 independent tasks occupying 8 kilo-bytes of eprom. The software was written to perform all terminal interaction and editing in order to reduce the host CPU involvement to a single interrupt per record. The resultant interface proved capable of handling an aggregate throughput in excess of 4000 characters per second which was sufficient to cope with all four terminals running at 9600 bits per second, even when all four were transferring in burst mode. The interface also proved to be between five and eighteen times less demanding on the host than the two standard Hewlett Packard interfaces then available. When compared to the low cost HP12531 interface, the multiplexer increased the 9600b/s terminal handling capability of the host from 3 terminals to 52. / Thesis (M.Sc.-Electronic Engineering)-University of Natal, 1987.

A Zenith-386 workstation was outfitted with a DICRES-54.8 paralell port board to facilitate I/C between a large Summagrid x-y coordinate digital measurement pad that has a resolution of 10 microns. Film views of high energy particle collisions can be projected onto this pad for measurement. Voice prompts via a Votrax speech synthesis system are sent at critical points during the algorithm from the Z-386 through other ports of the DICRES board. Progress in measurement is fed into the Z-386's serial port from an Interstate voice recognition system at other points of the measurement algorithm. The whole measurement process is managed by an assembler language based modular computer program. / Department of Physics and Astronomy

This thesis aims to explore how to physically interact with computational models on an interactive tabletop display. The research began with the design and implementation of several prototype systems. The research of the prototype systems showed that tangible interactions on interactive tabletops have the potential to be more effective on some tasks than traditional interfaces that use screen displays, keyboards and mice. The prototype work shaped the research to focus on the effectiveness of adopting tangible interactions on interactive tabletops. To substantiate the thesis claims, this thesis develops an interactive tabletop application, Pathways, to support the fitting process in modeling biological systems. Pathways supports the concepts of Tangible User Interfaces (TUIs) and tabletop visualizations. It realizes real-time simulation of models and provides comparisons of simulation results with experimental data on the tabletop. It also visualizes the simulation of the model with animations. In addition to that, Pathways introduces a new visualization to help systems biologists quickly compare the simulation results. This thesis provides the quantitative and qualitative evaluation results of Pathways. The evidence showed that using tangible interactions to control numerical values is practical. The results also showed that in experimental conditions users achieved better fitting results and faster fitting results on Pathways than the control group, which used the systems biologists' current tools. The results further suggested that it is possible to recruit non-experts to perform the fitting tasks that are usually done by professional systems biologists.

Bibliography: p. 199-207. Describes the basis of a theoretical and experimental project, directed at the design and evaluation of a practical active noise control system suitable for a single light engine aircraft. The performance of virtual sensors were evaluated both analytically and experimentally in progressively more complex environments to identify their capabilities and limitations.

Security is a primary concern in this era of pervasive computing. Hardware based security mechanisms facilitate the construction of trustworthy secure systems; however, existing hardware security approaches require modifications to the micro-architecture of the processor and such changes are extremely time consuming and expensive to test and implement. Additionally, they incorporate cryptographic security mechanisms that are computationally intensive and account for excessive energy consumption, which significantly degrades the performance of the system. In this dissertation, I explore the domain of hardware based security approaches with an objective to overcome the issues that impede their usability. I have proposed viable solutions to successfully test and implement hardware security mechanisms in real world computing systems. Moreover, with an emphasis on cryptographic memory integrity verification technique and embedded systems as the target application, I have presented energy efficient architectures that considerably reduce the energy consumption of the security mechanisms, thereby improving the performance of the system. The detailed simulation results show that the average energy savings are in the range of 36% to 99% during the memory integrity verification phase, whereas the total power savings of the entire embedded processor are approximately 57%.

Hardware/Software (HW/SW) interfaces are pervasive in modern computer systems. Most of HW/SW interfaces are implemented by devices and their device drivers. Unfortunately, HW/SW interfaces are unreliable and insecure due to their intrinsic complexity and error-prone nature. Moreover, assuring HW/SW interface reliability and security is challenging. First, at the post-silicon validation stage, HW/SW integration validation is largely an ad-hoc and time-consuming process. Second, at the system deployment stage, transient hardware failures and malicious attacks make HW/SW interfaces vulnerable even after intensive testing and validation. In this dissertation, we present a comprehensive solution for HW/SW interface assurance over the system life cycle. This solution is composited of two major parts. First, our solution provides a systematic HW/SW co-validation framework which validates hardware and software together; Second, based on the co-validation framework, we design two schemes for assuring HW/SW interfaces over the system life cycle: (1) post-silicon HW/SW co-validation at the post-silicon validation stage; (2) HW/SW co-monitoring at the system deployment stage. Our HW/SW co-validation framework employs a key technique, conformance checking which checks the interface conformance between the device and its reference model. Furthermore, property checking is carried out to verify system properties over the interactions between the reference model and the driver. Based on the conformance between the reference model and the device, properties hold on the reference model/driver interface also hold on the device/driver interface. Conformance checking discovers inconsistencies between the device and its reference model thereby validating device interface implementations of both sides. Property checking detects both device and driver violations of HW/SW interface protocols. By detecting device and driver errors, our co-validation approach provides a systematic and ecient way to validate HW/SW interfaces. We developed two software tools which implement the two assurance schemes: DCC (Device Conformance Checker), a co-validation framework for post-silicon HW/SW integration validation; and CoMon (HW/SW Co-monitoring), a runtime verication framework for detecting bugs and malicious attacks across HW/SW interfaces. The two software tools lead to discovery of 42 bugs from four industry hardware devices, the device drivers, and their reference models. The results have demonstrated the signicance of our approach in HW/SW interface assurance of industry applications.

The rapidly increasing complexities of hardware designs are forcing design methodologies and tools to move to the Electronic System Level (ESL), a higher abstraction level with better productivity than the state-of-the-art Register Transfer Level (RTL). Behavioral synthesis, which automatically synthesizes ESL behavioral specifications to RTL implementations, plays a central role in this transition. However, since behavioral synthesis is a complex and error-prone translation process, the lack of designers' confidence in its correctness becomes a major barrier to its wide adoption. Therefore, techniques for establishing equivalence between an ESL specification and its synthesized RTL implementation are critical to bring behavioral synthesis into practice. The major research challenge to equivalence checking for behavioral synthesis is the significant semantic gap between ESL and RTL. The semantics of ESL involve untimed, sequential execution; however, the semantics of RTL involve timed, concurrent execution. We propose a sequential equivalence checking (SEC) framework for certifying a behavioral synthesis flow, which exploits information on successive intermediate design representations produced by the synthesis flow to bridge the semantic gap. In particular, the intermediate design representation after scheduling and pipelining transformations permits effective correspondence of internal operations between this design representation and the synthesized RTL implementation, enabling scalable, compositional equivalence checking. Certifications of loop and function pipelining transformations are possible by a combination of theorem proving and SEC through exploiting pipeline generation information from the synthesis flow (e.g., the iteration interval of a generated pipeline). The complexity brought by bubbles in function pipelines is creatively reduced by symbolically encoding all possible bubble insertions in one pipelined design representation. The result of this dissertation is a robust, practical, and scalable framework for certifying RTL designs synthesized from ESL specifications. We have validated the robustness, practicality, and scalability of our approach on industrial-scale ESL designs that result in tens of thousands of lines of RTL implementations.