In an effort to lower interconnect time delays and power dissipation in highly integrated logic and memory nanoelectronic products, numerous changes in the materials and processes utilized to fabricate the interconnect have been made in the past decade. Chief among these changes has been the replacement of aluminum (Al) by copper (Cu) as the interconnect metal and the replacement of silicon dioxide (SiO2) by so called low dielectric constant (low-k) materials as the insulating interlayer dielectric (ILD). Cu/low-k structure significantly decreases the RC delay compared with the traditional interconnect (Al/SiO₂). Therefore, the implementation of low-k dielectric in Cu interconnect structures has become one of the key subjects in the microelectronics industry. Incorporation of pores into the existing low-k dielectric is a favorable approach to achieve ultra low-k ILD materials. To bring memory and logic closer together is an effective approach to remove the latency constraints in metal interconnects. The resistive random access memories (RRAM) technology can be integrated into a complementary metal-oxide-semiconductor (CMOS) metal interconnect structure using standard processes employed in back-end-of-line (BEOL) interconnect fabrication. Based on this premise, the study of this thesis aims at assessing a possible co-integration of resistive switching (RS) cells with current BEOL technology. In particular, the issue is whether RS can be realized with porous dielectrics, and if so, what is the electrical characterization of porous low-k/Cu interconnect-RS devices with varying percentages of porosity, and the diffusive and drift transport mechanism of Cu across the porous dielectric under high electric fields. This work addresses following three areas: 1. Suitability of porous dielectrics for resistive switching memory cells. The porous dielectrics of various porosity levels have been supplied for this work by Intel Inc. In course of the study, it has been found that Cu diffusion and Cu+ ion drift in porous materials can be significantly different from the corresponding properties in non-porous materials with the same material matrix. 2. Suitability of ruthenium as an inert electrode in resistive switching memory cells. Current state-of-the-art thin Cobalt (Co)/Tantalum Nitride (TaN) bilayer liner with physical vapor deposited (PVD) Cu-seed layer has been implemented for BEOL Cu/low-k interconnects. TaN is used for the barrier and Co is used to form the liner as well as promoting continuity for the Cu seed. Also, the feasibility of depositing thin CVD ruthenium (Ru) liners in BEOL metallization schemes has been evaluated. For this study, Ru is used as a liner instead of Ta or Co in BEOL interconnects to demonstrate whether it can be a potential candidate for replacing PVD-based TaN/Ta(Co)/Cu low-k technology. In this context, it is of interest to investigate how Ru would perform in well-characterized RS cell, like Cu/TaOx/Ru, given the fact that Cu/TaOx/Pt device have been proven to be good CBRAM device due to its excellent unipolar and bipolar switching characteristics, device performance, retention, reliability. If Cu/TaOx/Ru device displays satisfactory resistive switching behavior, Cu/porous low-k dielectric/Ru structure could be an excellent candidate as resistive switching memory above the logic circuits in the CMOS back-end. 3. Potential of so-called covalent dielectric materials for BEOL deployment and possibly as dielectric layer in the resistive switching cells. The BEOL reliability is tied to time dependent failure that occurs inside dielectric between metal lines. Assessing the suitability of covalent dielectrics for back-end metallization is therefore an interesting topic. TDDB measurements have been performed on pure covalent materials, low-k dielectric MIM and MI-semiconductor (MIS) devices supplied by Intel Inc. / Master of Science / While the scaling of conventional memories based on floating gate MOSFETs is getting increasingly difficult, novel types of non-volatile memories, such as resistive-switching memories, have recently been of interest to both industry and academia. Resistive switching memory is being considered for next-generation non-volatile memory due to relatively high switching speed, high scalability, low power consumption, good retention and simple structure. Additionally, these twoterminal devices operate by changing resistance from high resistance OFF-state (HRS) to low resistance ON-state (LRS) in response to applied voltage or current due to the formation and rupture of a conductive filament. In particular, Conductive Bridging Random Access Memory (CBRAM), also referred as Programmable Metallization Cell (PMC), is a promising candidate for a resistive memory device due to its highly scalable and low-cost technology. Currently, the interconnect RC scaling methods have reached their limits and there is an urgent need for alternative ways to reduce or remove the latency constraints in CMOS low-k/Cu interconnect. One method is building CBRAM directly into a low-k/Cu interconnects to reduce the latency in connectivity constrained computational devices and the chip’s footprint by stacking memory on top of logic circuits. This is possible since the Cu metal lines and low-k/Cu interconnect already prefigure a potential RS device. This work addresses three areas: Firstly, the suitability of porous dielectrics for resistive switching memory cells. Secondly, the suitability of ruthenium as an inert electrode in resistive switching memory cells. If Ru resistive memory device displays satisfactory resistive switching behavior, Cu/porous low-k dielectric/Ru structure could be an excellent candidate as resistive switching memory above the logic circuits in the CMOS back-end-of-line (BEOL). Thirdly, the potential of so-called covalent dielectric materials for BEOL deployment and possibly as dielectric layer in the resistive switching cells.

京都大学 / 0048 / 新制・論文博士 / 博士(工学) / 乙第13240号 / 論工博第4178号 / 新制||工||1720(附属図書館) / (主査)教授 木本 恒暢, 教授 藤田 静雄, 教授 山田 啓文 / 学位規則第4条第2項該当 / Doctor of Philosophy (Engineering) / Kyoto University / DFAM

Emerging memory technologies are being intensively investigated for extending Moore\'s law in the next decade. The conductive bridge random access memory (CBRAM) is one of the most promising candidates. CBRAM shows unique nanoionics-based filamentary switching mechanism. Compared to flash memory, the advantages of CBRAM include excellent scalability, low power consumption, high OFF-/ON-state resistance ratio, good endurance, and long retention. Besides the nonvolatile memory applications, resistive switching devices implement the function of memristor which is the fourth basic electrical component. This research presents the characterization and modeling of Cu/TaOx/Pt resistive switching devices. Both Cu and oxygen vacancy nanofilaments can conduct current according to the polarity of bias voltage. The volatile resistive switching phenomenon has been observed on Cu/TaOx/delta-Cu/Pt devices and explained by a flux balancing model. The resistive devices are also connected in series and in anti-parallel manner. These circuit elements are tested for chaotic neural circuit. The quantum conduction has been observed in the I-V characteristics of devices, evidencing the metallic contact between the nanofilament and electrodes. The model of filament radial growth has been developed to explain the transient I-V relation and multilevel switching in the metallic contact regime. The electroforming/SET and RESET processes have been simulated according to the mechanism of conductive filament formation and rupture and validated by experimental results. The Joule and Thomson heating effects have also been investigated for the RESET processes. / Ph. D.

While the scaling of conventional memories based on floating gate MOSFETs is getting increasingly difficult, novel type of non-volatile memories, such as resistive switching memories, have lately found increased attention by both industry and academia. Resistive switching memory (ReRAM) is being considered one of the prime candidates for next-generation non-volatile memory due to relatively high switching speed, superior scalability, low power consumption, good retention and simplicity of its structure which does not require the expensive real estate structure of the silicon substrate. Furthermore, integration of ReRAM directly into a CMOS low-k/Cu interconnect module would not only reduce latency in connectivity constrained devices, but also would reduce chip's footprint by stacking memory layers on top of the logic circuits. One good candidate is the well-behaved Cu/TaOx/Pt resistive switching device. However, since platinum (Pt) acting as the inert electrode is not an economic choice for industrial production, a Back End of Line (BEOL)-compatible replacement of Pt is highly desirable. A systematic investigation has been conducted and metals such as Ru, Rh and Ir are found to be the best potential candidates to supplant Pt. The device properties of Ru, Rh and Ir based resistive switching devices have been explored in this work. However, the challenges of implementing ReRAM cell into BEOL of CMOS encompass not only the choice of materials of a CBRAM cell proper, but also the way the cell is embedded within BEOL. In case of the inert electrode, the metal interfacing the solid electrolyte (e.g. TaOx) has to be supplanted by a glue layer, and heat transport layer, leading to an engineering task of a composite electrode beyond the requirements of low miscibility with, and low surface diffusivity of the inert electrode with respect of the active metal atoms released by the active electrode (here Cu). The metal of the active electrode (Cu, Ag, Ni) is required to allow for a copious redox reaction but simultaneously preventing reactions with the dielectric. Finally, for the solid electrolyte, a dielectric with a moderate level of defects is preferred which may be controlled, for example by the deposition processes modulating the stoichiometry of the material. This research study begins with exploration of several devices derived from the benchmark device Cu/TaOx/Pt and manufacturing those in Micron nanofabrication and characterization laboratory at Virginia Tech with the latter device used as a benchmark for performance assessment. Electric characterization of the manufactured Cu/TaOx/Ru devices has shown some notable differences between them due to the different formation, shape and rupture of the conductive filament. The inferior switching properties of the Ru device have been attributed to the substantially degraded inertness properties of the Ru electrode as a stopping barrier for Cu as compared to the Pt electrode. To study this degradation effect further, two nominally identical devices however differently embedded on the Si wafer have been fabricated. The electric behavior of the two devices are found to be markedly different and is attributed to the difference in high local temperatures in the device during the switching that cause species interlayer diffusion and trigger undesired chemical reactions. Thus, the embedment of the device has a foremost impact on the intrinsic device performance. To investigate the impact of inert electrode on the endurance of ReRAM memory cells, baseline device Cu/TaOx/Pt/Ti is compared with six devices manufactured with different inert electrode constructions: Pt/Cr, Rh/Cr, Rh/Ti, Rh/Al2O3, Ir/Ti, and Ir/Cr, while the Cu electrode and the TaOx dielectric are identical. Although the glue layers Ti, Cr or Al2O3 are not an inherent part of the device proper, they have a tangible impact on the device endurance as well. It is experimentally demonstrated that inert electrodes with high thermal conductivities have superior endurance properties over an electrode with low thermal conductivity and the heat conductivity of inert electrode has a substantial impact on ReRAM cell performance. Since reset operation is a thermally driven process, frequent switching of resistive memory cell leads to a local accumulation of Joules heat, especially when the switching rate is faster than the heat removal rate. This investigation of local heating effects led to the exploration of non-local heat transfer within a memory array. In a crossbar arranged ReRAM cell array, heat generated in one device spreads via common electrode metal lines to the neighboring cells causing their performance degradation constituting non-local heat transfer mechanism leading to performance deterioration of neighboring cells. In addition to the electrical characterization of devices affected by the remote heat transfer, novel cell array architectures have been proposed and investigated with the goal to significantly mitigate the cell-to-cell thermal crosstalk. One of the possible mitigation measures would be modified cell erasure algorithm. / Doctor of Philosophy / Emerging memory technologies are being intensively investigated for extending Moore's scaling law in the next decade. The resistive random-access memory (ReRAM) is one of the most propitious contenders to replace the current ubiquitous FLASH memory. ReRAM shows unique nanoionics based filamentary switching mechanism. Compared to the current nonvolatile memory based on floating gate MOSFET transistor, the advantages of ReRAM include superior scalability, low power consumption, high OFF-/ON-state resistance ratio, excellent endurance, and long retention of the logic bit states. Besides the nonvolatile memory applications, resistive switching devices implement the function of a memristor which is the fourth basic electrical component and can be used for neuromorphic computing. A ReRAM device is in essence a metal-insulator-metal structure. One of the metal electrodes is called the active electrode and provides the building material for the filamentary connection between the electrodes. An important requirement of the second electrode, called the inert electrode, is to be immiscible with the metal atoms of the active electrode and to exhibit a minimum of susceptibility to structural changes and chemical reactions. This research presents a thorough investigation of the role and properties of the inert electrode and offers guideline for the optimal selection of the inert electrode in a commercially viable product. It has been found out that one important property of the inert electrode is its heat conductivity and also the way the inert electrode is embedded on a substrate. Consequently, the concept of the inert electrode has been replaced by the concept of engineered inert electrode module which evolved from a single metal layer to a multilayer stack displaying glue layers, high thermal conductivity layers dissipating the heat quickly, and diffusion stop layers eliminating unwanted chemical reactions. The investigation of the electro-thermal effects led to the discovery of the cell-to-cell thermal cross talk within the memory array which can seriously affect the performance of cells impacted by the remote heat transfer. When a memory cell is switched repeatedly a considerable amount of heat is dissipated in the cell and the heat may spread to neighboring cells that share the same metal lines. This heat transfer causes degradation of electrical performance of the neighboring cells. A method has been developed to characterize quantitatively how the electrical performance is affected by the thermal cross-talk impacting the electric performance of neighboring cells. Several novel mitigation strategies of new memory array architectures have been proposed and investigated.

Resistive random access memory (RRAM), based on a two-terminal resistive switching device with a switching element sandwiched between two electrodes, has been an attractive candidate to replace flash memory owing to its simple structure, excellent scaling potential, low power consumption, high switching speed, and good retention and endurance properties. However, due to the current limited understanding of the device mechanism, RRAMs research are still facing several issues and challenges including instability of operation parameters, the relatively high reset current, the limited retention and the unsatisfactory endurance. In this study, we investigated the switching mechanisms, conditions and applications of oxygen vacancy (Vo) filament formation in resistive memories. By studying the behavior of conductive Vo nanofilaments in several metal/oxide/metal resistive devices of various thicknesses of oxides, a resulting model supported by the data postulates that there are two distinct modes of creating oxygen vacancies: i) a conventional bulk mode creation, and ii) surface mode of creating oxygen vacancies at the active metal-dielectric interface. A further investigation of conduction mechanism for the Vo CF only based memories is conducted through insertion of a thin layer of titanium into a Pt/ Ta2O5/Pt structure to form a Pt/Ti/ Ta2O5/Pt device. A space charge limited (SCL) conduction model is used to explain the experimental data regarding SET process at low voltage ranges. The evidence for existence of composite copper/oxygen vacancy nanofilaments is presented. The innovative use of hybrid Vo/Cu nanofilament will potentially overcome high forming voltage and gas accumulation issues. A resistive floating electrode device (RFED) is designed to allow the generation of current/voltage pulses that can be controlled by three independent technology parameters. Our recent research has demonstrated that in a Cu/TaOx/Pt resistive device multiple Cu conductive nanofilaments can be formed and ruptured successively. Near the end of the study, quantized and partial quantized conductance is observed at room temperature in metal-insulator-metal structures with graphene submicron-sized nanoplatelets embedded in a 3-hexylthiophene (P3HT) polymer layer. As an organic memory, the device exhibits reliable memory operation with an ON/OFF ratio of more than 10. / Ph. D.

Owing to its excellent scaling potential, low power consumption, high switching speed, and good retention, and endurance properties, Resistive Random Access Memory (RRAM) is one of the prime candidates to supplant current Nonvolatile Memory (NVM) based on the floating gate (FG) MOSFET transistor, which is at the end of its scaling capability. The RRAM technology comprises two subcategories: 1) the resistive phase change memory (PCM), which has been very recently deployed commercially, and 2) the filamentary conductive bridge RAM (CBRAM) which holds the promise of even better scaling potential, less power consumption, and faster access times. This thesis focuses on several aspects of the CBRAM technology. CBRAM devices are based on nanoionics transport and chemo-physical reactions to create filamentary conductive paths across a dielectric sandwiched between two metal electrodes. These nano-size filaments can be formed and ruptured reliably and repeatedly by application of appropriate voltages. Although, there exists a large body of literature on this topic, many aspects of the CBRAM mechanisms and are still poorly understood. In the next paragraph, the aspects of CBRAM studied in this thesis are spelled out in more detail. CBRAM cell is not only an attractive candidate for a memory cell but is also a good implementation of a new circuit element, called memristor, as postulated by Leon Chua. Basically, a memristor, is a resistor with a memory. Such an element holds the promise to mimic neurological switching of neuron and synapses in human brain that are much more efficient than the Neuman computer architecture with its current CMOS logic technology. A memristive circuitry can possibly lead to much more powerful neural computers in the future. In the course of the research undertaken in this thesis, many memristive properties of the resistive cells have been found and used in models to describe the behavior of the resistive switching devices. The research performed in this study has also an immediate commercial application. Currently, the semiconductor industry is faced with so-called latency scaling dilemma. In the past, the bottleneck for the signal propagation was the time delay of the transistor. Today, the transistors became so fast that the bottleneck for the signal propagation is now the RC time delay of the interconnecting metal lines. Scaling drives both, resistance and parasitic capacitance of the metal lines to very high values. In this context, one observes that resistive switching memory does not require a Si substrate. It is therefore an excellent candidate for its implementation as an o n-chip memory above the logic circuits in the CMOS back-end, thus making the signal paths between logic and memory extremely short. In the framework of a Semiconductor Research Corporation (SRC) project with Intel Corporation, this thesis investigated the breakdown and resistive switching properties of currently deployed low k interlayer dielectrics to understand the mechanisms and potential of different material choices for a realization of an RRAM memory to be implemented in the back-end of a CMOS process flow. / Master of Science

付記する学位プログラム名: 京都大学卓越大学院プログラム「先端光・電子デバイス創成学」 / 京都大学 / 新制・課程博士 / 博士(工学) / 甲第24622号 / 工博第5128号 / 新制||工||1980(附属図書館) / 京都大学大学院工学研究科電子工学専攻 / (主査)教授 木本 恒暢, 教授 白石 誠司, 准教授 小林 圭 / 学位規則第4条第1項該当 / Doctor of Philosophy (Engineering) / Kyoto University / DFAM

La mémoire NAND Flash représente une part importante dans le marché des circuits intégrés et a bénéficié de la traditionnelle miniaturisation de l’industrie des sémiconducteurs lui permettant un niveau d’intégration élevé. Toutefois, cette miniaturisation semble poser des sérieux problèmes au-delà du noeud 22 nm. Dans un souci de dépasser cette limite, des solutions mémoires alternatives sont proposées parmi lesquelles la mémoire résistive (RRAM) se pose comme un sérieux candidat pour le remplacement de NAND Flash. Ainsi, dans cette thèse nous essayons de répondre à des nombreuses questions ouvertes sur les dispositifs RRAM à base d’oxyde d’hafnium (HfO2) en particulier en adressant le manque de compréhension physique détaillée sur leur fonctionnement et leur fiabilité. L’impact de la réduction de taille des RRAM, le rôle des électrodes et le processus de formation et de diffusion des défauts sont étudiés. L’impact de l’alliage/dopage de HfO2 avec d’autres matériaux pour l’optimisation des RRAM est aussi abordé. Enfin, notre étude tente de donner quelques réponses sur la formation du filament conducteur, sa stabilité et sa possible composition. / Among non-volatile memory technologies, NAND Flash represents a significant portion in the IC market and has benefitted from the traditional scaling of semiconductor industry allowing its high density integration. However, this scaling seems to be problematic beyond the 22 nm node. In an effort to go beyond this scaling limitation, alternative memory solutions are proposed among which Resistive RAM (RRAM) stands out as a serious candidate for NAND Flash replacement. Hence, in this PhD thesis we try to respond to many open questions about RRAM devices based on hafnium oxide (HfO2), in particular, by addressing the lack of detailed physical comprehension about their operation and reliability. The impact of scaling, the role of electrodes, the process of defects formation and diffusion are investigated. The impact of alloying/doping HfO2 with other materials for improved RRAM performance is also studied. Finally, our study attempts to provide some answers on the conductive filament formation, its stability and possible composition.