A radix-based calibration technique was previously proposed with a two-stage algorithmic analog-to-digital converter (ADC). The objective of this work is to verify the capability of radix-based calibration for a true multi-stage ADC. In order to prove the idea, a single bit-per-stage, 20-stage pipelined ADC is designed in a 0.35-��m CMOS technology. The system is fully differential and requires two non-overlapping clock phases to operate. The implementation of the calibration technique in the pipelined ADC is investigated. Simulation results show that 109dB of SNDR, 112dB of THD, and 116dB of SFDR can be achieved, which indicates the overall accuracy of the ADC is 18 bits. / Graduation date: 2003

Oversampling and noise-shaping methods for digital-to-analog (D/A) conversion have been widely accepted as methods of choice in high performance data conversion applications. In this thesis, the fundamentals of D/A conversion and oversampling D/A conversion were discussed, along with the detailed analysis and comparison of the reported state-of-the-art oversampling D/A converters. Conventional oversampling D/A converters use 1-bit internal D/A conversion. Complex analog filters and/or large oversampling ratios are usually needed in these 1-bit oversampling D/A converters. Using multi-bit internal D/A conversion, the analog filter can be much simpler and the oversampling ratio can be greatly reduced. However, the linearity of the multi-bit D/A converter has to be at least the same as that required by the overall system. The dual-quantization technique developed in the course of this research provides a good alternative for implementing multi-bit oversampling D/A converters. The system uses two internal D/A converters; one is single-bit and the other is multi-bit. The single-bit D/A converter is used in a path called the signal path while the multi-bit D/A converter is used in a path called the correction path. Since the multi-bit D/A converter is not directly placed in the signal path, its nonlinearity error can be noise shaped by an analog differentiator so that the in-band noise contribution from the nonlinearity error is very small at the system output, greatly reducing the linearity requirement on the multi-bit internal D/A converter. An experimental implementation of an oversampling D/A converter using the dual-quantization technique was carried out to verify the concept. Despite about 10 dB higher noise than expected and the high second-order harmonic distortion due to practical problems in the implementation, the implemented system showed that the corrected output had more than 20 dB improvement over the uncorrected output in both signal-to-noise ratio and dynamic range, demonstrating the validity of the concept. / Graduation date: 1996

This thesis describes the development of a flash analog-to-digital converter based on current-mode technique. The advantages of current -mode technique are higher speed, smaller chip area, and simple division of reference current based on current mirror. A current-mode comparator is designed consisting of a cascode current mirror and a current sense amplifier used as a latch. The new method allows effective and simple high-speed A/D conversion where the input is a current signal and the output of the latch is a digital voltage signal. A four-bit flash analog-to-digital converter, using current sense amplifier comparator is designed and simulated in 1-micron CMOS technology. Simulation results show that for ADC with resolution below six-bit, this technique offers a comparable accuracy with the existing voltage-mode methods at much higher speed. / Graduation date: 1993

Oversampled data converters are becoming increasingly popular for high-precision data conversion. There have been many publications on oversampled analog-to-digital (A/D) converters but relatively few on oversampled digital-to-analog (D/A) converters. In this thesis, issues concerning the analysis and design of the oversampled D/A converters are addressed. Simulation tools and analytical methods are discussed. A novel dual-quantization technique for achieving high-precision D/A conversion is proposed. A design example is presented to demonstrate that in many aspects the proposed technique is superior to existing techniques. The thesis is divided into four chapters. Chapter 1 is an introduction to the general concepts of Nyquist-rate and oversampled data converters. Chapter 2 describes some building blocks to be used in oversampled D/A converters and gives both theoretical and simulation methods for analzying them. Chapter 3 describes the proposed dual-quantization D/A converters, including the structure, the associated design issues and an example to verify the validity of this technique. Finally, Chapter 4 summarizes the properties of the simulated system and proposes some future research work. / Graduation date: 1992

This thesis presents a new family of converters for high power interconnection of dc buses with different voltage levels. Proposed converters achieve high voltage dc-dc conversion without an intermediate ac conversion stage. This function is implemented without series connection of active switches, or the use of isolation transformers. The salient features of proposed converters are (i) design and construction simplicity, (ii) low switching losses through soft turn-on and soft turn-off, (iii) single stage dc-dc conversion without high-current chopping, (iv) modular structure, (v) equal voltage sharing among the converter modules. Three converter circuits are investigated. The first performs unidirectional power transfer from a dc bus with higher voltage to a dc bus with lower voltage. The second performs unidirectional power transfer from a dc bus with lower voltage to a dc bus with higher voltage. Both converters are suitable for interconnecting single pole dc buses with same polarity, or double pole dc buses. A third converter is also presented which performs the function of either the first or the second converter with polarity reversal. The third converter is suitable for interconnecting single pole dc buses with different polarities, or double pole dc buses. By hybrid integration of the proposed three converters, the thesis also investigates other topologies for bidirectional power transfer between two dc buses. Proposed converters operate only in discontinuous conduction mode and exhibit soft switching operation for the active and passive switches. A common feature between the proposed converters is the self current turn-off for the active switches at zero voltage. This allows the use of thyristors as active switches alleviating their reverse recovery losses. For each converter topology, the structure is presented, its operation principle is explained and a complete set of design equations are derived. Comparisons are performed on high-power and high-voltage design examples. The merits and limitations of each converter are concluded. Practical considerations regarding components selection, loss analysis, filter design and the non-idealities of the circuits are studied. Experimental implementation of scaled-down laboratory prototypes is presented to provide a proof of concept and validate the operation principle of the proposed converter topologies.

This thesis presents a new family of converters for high power interconnection of dc buses with different voltage levels. Proposed converters achieve high voltage dc-dc conversion without an intermediate ac conversion stage. This function is implemented without series connection of active switches, or the use of isolation transformers. The salient features of proposed converters are (i) design and construction simplicity, (ii) low switching losses through soft turn-on and soft turn-off, (iii) single stage dc-dc conversion without high-current chopping, (iv) modular structure, (v) equal voltage sharing among the converter modules. Three converter circuits are investigated. The first performs unidirectional power transfer from a dc bus with higher voltage to a dc bus with lower voltage. The second performs unidirectional power transfer from a dc bus with lower voltage to a dc bus with higher voltage. Both converters are suitable for interconnecting single pole dc buses with same polarity, or double pole dc buses. A third converter is also presented which performs the function of either the first or the second converter with polarity reversal. The third converter is suitable for interconnecting single pole dc buses with different polarities, or double pole dc buses. By hybrid integration of the proposed three converters, the thesis also investigates other topologies for bidirectional power transfer between two dc buses. Proposed converters operate only in discontinuous conduction mode and exhibit soft switching operation for the active and passive switches. A common feature between the proposed converters is the self current turn-off for the active switches at zero voltage. This allows the use of thyristors as active switches alleviating their reverse recovery losses. For each converter topology, the structure is presented, its operation principle is explained and a complete set of design equations are derived. Comparisons are performed on high-power and high-voltage design examples. The merits and limitations of each converter are concluded. Practical considerations regarding components selection, loss analysis, filter design and the non-idealities of the circuits are studied. Experimental implementation of scaled-down laboratory prototypes is presented to provide a proof of concept and validate the operation principle of the proposed converter topologies.

This thesis presents the design of a 10 bit Analog to Digital Converter which consists of a 6 bit flash followed by a 4 bit pipeline architecture. The total system is described and the 4 bit pipeline is implemented on a bipolar process. The objective of this research is to provide an alternative approach to high speed ADC designs and to implement a pipeline ADC which samples at greater speeds than those achieved with presently existing CMOS pipeline designs. This paper presents the complete architecture, the cell design and simulated performance for each block in the pipeline, and the measured results for the four bit pipeline implementation. / Graduation date: 1993

In the present study, the corrosion behaviour of several magnesia-chrome (MC) and magnesia-alumina spinel (MA) bricks against fayalite type slags was investigated and the role of the spinel phases was highlighted. The experimental results revealed that the corrosion resistance of the MC bricks was superior to the MA bricks against KIVCET slags in static and dynamic conditions. As a result of the interaction between MgO from MC bricks and the slag, a modified forsterite phase (Mg, Fe, Zn, Ca) ���SiO��� was formed, which destroyed the precipitated complex spinel bonds at the grain boundaries of periclase and magnesia-chromia spinel. Furthermore, both MgO and MgO-MgAl���O��� spinel in the MA brick dissolved into the slag, which resulted in modified forsterite phases of (Mg, Fe, Zn, Ca)���SiO��� and (Mg, Fe, Zn)(Fe, Al)���0��� complex spinels, respectively. In addition, the accretion formation in the KIVCET furnace was investigated through solubility experiments of Cr���0��� in the KIVCET slag with various amounts of lead, which revealed that the net contribution of Cr���03 to the spinel formation is the highest in the barren (no Pb) slag, followed by high-lead (11% Pb) and it is the lowest for the low-lead (6% Pb) slag. The amount of spinel solid solution increased consistently with increasing Cr���0��� dissolved and the PbO existent in the slag. From examinations of several used bricks from the tuyere area of a Peirce Smith nickel converter, it was found that the corrosion is due to the interaction of the partially oxidized matte penetrating deep into the brick and the magnesia grains forming (Mg, Fe, Ni, Co) XOy spinels. Analyses of brick samples used in the KIVCET Electric Furnace roof identified deep reaching sulphation, which weakened the bonding phase between coarse magnesia grains. In the Bottom Blown Oxygen Converter, a highly aggressive lead and bismuth oxide rich slag penetrated deep into the brick, which destroyed the grain boundaries, causing the refractory to be easily eroded at the refractory-slag interface. Our studies concluded that the spinel phases, either as magnesium chromate, magnesium aluminate or complex spinel [(Mg, Fe)(Cr, Al, Fe) ���O���], enhanced the corrosion resistance of a basic refractory to fayalite type slags from the non-ferrous smelting and converting furnaces.

Thesis (M.S. in electrical engineering)--Washington State University, December 2009. / Title from PDF title page (viewed on Feb. 9, 2010). "School of Electrical Engineering and Computer Science." Includes bibliographical references (p. 42-43).

Thesis (M.S. in Electrical Engineering)--Naval Postgraduate School, June 2003. / Thesis advisor(s): Robert W. Ashton, Todd R. Weatherford. Includes bibliographical references (p. 83-84). Also available online.