Hand-written text recognition (HTR) is a transformative technology in recent years that significantly assists the study of historical documents, therefore, boosting digital humanity research. Conventional optical character recognition (OCR) technique is sensitive to certain writing styles and thus not adaptive. Our study attempts an adaptive pipeline that enables the HTR of Swedish hand-written documents which contributes to the study of Swedish history including the modern and contemporary democratization process with the Labour’s Memory dataset and Demokrati 100 dataset. This pipeline integrates transfer learning, fine-tuning techniques, and a novel confidence-based ensemble strategy to reduce the transcribing error rate. Our findings demonstrate the efficacy of these strategies in significantly improving performance metrics. Results indicate a substantial reduction in transcribing error rate compared to baseline methods. Notably, our transfer learning model achieves a Character Error Rate (CER) of 6.664%. The introduction of a confidence-based ensemble strategy yields a CER of 5.976%, outperforming any individual model and the baseline significantly. We further propose optimizations in transfer learning by identifying that fine-tuning only recurrent and dense layers balances performance and computational efficiency. This approach enables a more time-efficient training process in case of a large dataset without compromising accuracy, offering practical benefits for real-world applications. Furthermore, our analysis reveals critical insights into the challenges of baseline detection and ground truth accuracy. We identify over-segmentation as a bottleneck in baseline detection and highlight the significance of addressing systematic errors in ground truth data.

During the development of complex embedded systems like controllers, conducting real-world testing can often be impractical due to factors such as cost, safety concerns, or unavailability during certain stages of development. In such scenarios, hardware-in-the-loop testing is a practical alternative. Hardware-in-the-loop testing involves interfacing the device under test with a simulation environment that mimics real-world inputs, enabling comprehensive testing without the associated risks or constraints. This thesis focuses on the transformation of a Matlab model depicting the behavior of a falling missile into VHDL. The purpose of this model is to integrate with an FPGA to facilitate real-time testing of control algorithm and associated hardware. The conversion successfully translated the Matlab model into VHDL, enabling execution within the constraints of the real-time system.  While the VHDL model closely mirrors the original Matlab model, minor deviations exist due to the discretisation process, resulting in slight discrepancies. However, suggestions on how to overcome these are proposed.

WebAssembly (Wasm) is an emerging technology for web development that has garnered significant popularity in web-based applications. It enables web browsers to execute codewritten in multiple languages seamlessly, delivering high performance across different platforms. With the introduction of The WebAssembly System Interface (WASI), facilitating the execution of Wasm beyond the confines of the web, Wasm is gaining traction in cloud computing as well. Recently, Docker introduced the support of running Wasm binaries in a container runtime using WasmEdge. This thesis investigates the performance implications and the usability benefits/issues of Wasm in container runtimes using WasmEdge compared to traditional Linux containers. To assess these aspects, two separate applications are utilized within the containers: the first application, inspired by the TPC-C benchmark, is created from the ground up to mimic a database workload, whereas the second application is WordPress, a widely adopted content management system. In evaluating the performance implications of Wasm containers, our experiments focus on gathering metrics relevant to container usage and management. These include image size, start-up times, CPU utilization, latency, and throughput differences between Wasm containers and traditional Linux containers. Additionally, we assess the usability of Wasm containers by examining aspects such as building, managing, deploying, portability, and language support. The finding of the thesis indicates that Wasm containers feature lower image sizes, up to 500% smaller image sizes than the Linux containers, and can improve cold-start times by 160%. However, due to the lack of multi-threading support of Wasm, the application performance becomes significantly degraded, resulting in increased latencies and reduced throughput compared to traditional containers. Furthermore, we underscore the portability advantage of Wasm containers over traditional ones in terms of usability. Nonetheless, the current language limitations of Wasm present more challenges than benefits compared totraditional containers.

Within the context of Industry 4.0, many devices have become more intelligent and connected, leading to challenges on how to meet the stringent requirements on latency and reliability in networks of critical cyber-physical systems. In particular, timely channel access and high reliability are of essence to guarantee real-time deadlines. To this end, time-division multiple-access (TDMA) schemes are often used in industrial applications to get contention-free access to the channel. Using pairwise non-orthogonal multiple access (NOMA) on top of such an existing TDMA scheme has recently emerged as a promising solution. With pairwise NOMA, two nodes are served simultaneously using the same time-frequency resources but with different power levels. To separate the signals, successive interference cancellation is used at the receiver. In addition, by adjusting the power allocation, pairwise NOMA can easily switch to TDMA by assigning zero power to one user, if and when needed. Due to this flexibility, pairwise NOMA can be integrated into existing wireless networks and schedulers with improved performance as a result. In particular, if pairwise NOMA could be tailored to the requirements of systems of collaborating cyber-physical systems, it would be possible to enhance performance in terms of latency and reliability, while still providing timely channel access to critical users using TDMA. This is the scope of the thesis work. In order to evaluate the communication reliability for each user in the system as well as for the overall system, the individual outage probability (IOP) and the overall outage probability (OOP) are of essence, but have so far not been available for pairwise NOMA used on top of TDMA. In this thesis work, closed-form expressions for the IOP and the OOP of both uplink and downlink NOMA are derived – also in the presence of a mobile smart jammer. Using these performance metrics, insightful guidelines on the impact of some key parameters on the communication reliability such as power allocation, decoding order, node placements and so on are provided. It should be noted that the conclusions on node placement can be used for smart user pairing, but also for placement of access points (AP) or even mobile APs, using a UAV. Moreover, by formulating a non-cooperative game between a malicious smart mobile jammer and a friendly mobile AP serving two friendly sensor nodes simultaneously, Nash equilibrium points are obtained to reduce power consumption for the AP, while satisfying the communication reliability requirements. Using the derived expressions for OOP and IOP to select proper settings for pairwise NOMA, it is shown that NOMA can be tailored to ensure user fairness, provide timely channel access and high reliability, which is useful for enhancing performance of critical cyber-physical systems even in the presence of jamming.

Den gemene svensken befinner sig allt oftare i digitala miljöer, inte minst i sociala medier. En inblick i dessa medier visar en mörkare sida som inkluderar kränkningar, sexuella trakasserier och andra kriminella handlingar. Snapchat är en av många samlingspunkter för dessa aktiviteter, bland annat för dess inbyggda funktion som automatiskt raderar meddelanden efter en viss tid. Men är datan verkligen raderad? Går det att skapa ett verktyg som gör det lika lätt att återställa datan som att radera den? Målet med denna uppsats är att utforska hur extraheringen av raderade meddelanden i Snapchat kan automatiseras, i syfte att underlätta IT-forensiska utredningar och minska IT-forensikerns höga arbetsbelastning. Resultatet visar att raderade meddelanden förekommer i filsystemet, med tillräcklig struktur för att ett skript ska kunna skrivas som automatiskt extraherar dessa tillsammans med resterande icke-raderade meddelanden. / <p>Källkod till programmet ReSnap:</p><p>https://github.com/8urle/ReSnap</p>

<p>The purpose of this Master’s Thesis is to produce a specification for the aircraft conflict alert system STCA, and implement a prototype as a module in the air traffic surveillance system NOVA9000. </p><p>The specification is constructed based on functional requirements from EUROCONTROL and describes a system using a nominal trajectory method, where the future paths of aircraft are estimated. The trajectory is created using a probabilistic approach, where future positions are described with probability fields. </p><p>The prototype is implemented using the specification with some simplifications. The prototype is evaluated using recorded traffic from a heavy air traffic region surrounding an airport with parallel runways. 15 alerts were induced in 1,5 hour of morning traffic; this is far too much to be acceptable. Improvements are proposed and explanations to the high rate of alerts are made.</p>

<p>This thesis evaluates and shows an implementation of a video telephony solution for network connected set-top boxes based on the SIP protocol for managing sessions. </p><p>Unlike other video telephony implementations the set-top box does not handle both audio and video, but only video. A separate phone is used to handle audio. To maintain compatibility with other video telephony implementations, which expect a single SIP device with both audio and video capabilities, a mechanism to merge the audio (SIP-phone) and video (set-top box) into a single entity was developed using a back-to-back user agent. </p><p>Due to the set-top boxes'limited hardware it could be impossible to have video compression and decompression performed by the set-top boxes. However, numerous performance tests of compression algorithms showed that the computational power available in the set-top boxes is sufficient to have acceptable frame rate and image quality in a video telephony session. A faster CPU or dedicated hardware for video compression and decompression would however be required in order to compete with dedicated video telephony systems available today. </p><p>The implemented video telephony system is based on open standards such as SIP, RTP and H.261, which means interoperability with other video telephony implementations, such as Microsoft's Windows Messenger 4.7, is good.</p>

<p>Nowadays, embedded systems are becoming more and more complex. For this reason, designers focus more and more to adopt component-based methods for their designs. Consequently, there is an increasing interest on modeling and verification issues of component-based embedded systems. </p><p>In this thesis, a tool, which integrates modeling, simulation and verification of component-based embedded systems, is designed and implemented. This tool uses the PRES+, Petri Net based Representation for Embedded Systems, to model component-based embedded systems. Both simulation and verification of systems are based on the PRES+ models. </p><p>This tool consists of three integrated sub-tools, each of them with a graphical interface, the PRES+ Modeling tool, the PRES+ Simulation tool and the PRES+ Verification tool. The PRES+ Modeling tool is a graphical editor, with which system designers can model component-based embedded systems easily. The PRES+ Simulation tool, which is used to validate systems, visualizes the execution of a model in an intuitive manner. The PRES+ Verification tool provides a convenient access to a model checker, in which models can be formally verified with respect to temporal logic formulas.</p>

<p>Systems controlled by embedded computers become indispensable in our lives and can be found in avionics, automotive industry, home appliances, medicine, telecommunication industry, mecatronics, space industry, etc. Fast, accurate and flexible performance estimation tools giving feedback to the designer in every design phase are a vital part of a design process capable to produce high quality designs of such embedded systems.</p><p>In the past decade, the limitations of models considering fixed task execution times have been acknowledged for large application classes within soft real-time systems. A more realistic model considers the tasks having varying execution times with given probability distributions. No restriction has been imposed in this thesis on the particular type of these functions. Considering such a model, with specified task execution time probability distribution functions, an important performance indicator of the system is the expected deadline miss ratio of tasks or task graphs.</p><p>This thesis proposes two approaches for obtaining this indicator in an analytic way. The first is an exact one while the second approach provides an approximate solution trading accuracy for analysis speed. While the first approach can efficiently be applied to monoprocessor systems, it can handle only very small multi-processor applications because of complexity reasons. The second approach, however, can successfully handle realistic multiprocessor applications. Experiments show the efficiency of the proposed techniques.</p> / Report code: LiU-Tek-Lic-2002:58.

Embedded systems are becoming increasingly common in our everyday lives. As technology progresses, these systems become more and more complex. Designers handle this increasing complexity by reusing existing components. At the same time, the systems must fulfill strict functional and non-functional requirements. This thesis presents novel and efficient techniques for the verification of component-based embedded system designs. As a common basis, these techniques have been developed using a Petri net based modelling approach, called PRES+. Two complementary problems are addressed: component verification and integration verification. With component verification the providers verify their components so that they function correctly if given inputs conforming to the assumptions imposed by the components on their environment. Two techniques for component verification are proposed in the thesis. The first technique enables formal verification of SystemC designs by translating them into the PRES+ representation. The second technique involves a simulation based approach into which formal methods are injected to boost verification efficiency. Provided that each individual component is verified and is guaranteed to function correctly, the components are interconnected to form a complete system. What remains to be verified is the interface logic, also called glue logic, and the interaction between components. Each glue logic and interface cannot be verified in isolation. It must be put into the context in which it is supposed to work. An appropriate environment must thus be derived from the components to which the glue logic is connected. This environment must capture the essential properties of the whole system with respect to the properties being verified. In this way, both the glue logic and the interaction of components through the glue logic are verified. The thesis presents algorithms for automatically creating such environments as well as the underlying theoretical framework and a step-by-step roadmap on how to apply these algorithms.