ITC/USA 2013 Conference Proceedings / The Forty-Ninth Annual International Telemetering Conference and Technical Exhibition / October 21-24, 2013 / Bally's Hotel & Convention Center, Las Vegas, NV / Constrained codes also known as modulation codes are a key component in the digital magnetic recording systems. The constrained codes forbid particular input data patterns which lead to some of the dominant error events or higher media noise. In data recording systems, a concatenated approach toward the constrained code and error-correcting code (ECC) is typically used and the decoding is done independently. In this paper, we show the improvement in combining the decoding of the constrained code and the ECC using generalized belief propagation (GBP) algorithm. We consider the performance of a combined modulation constraints and the ECC on a binary symmetric channel (BSC). We show that combining demodulation and decoding results in a superior performance compared to concatenated schemes. Furthermore, we compute the capacity of the joint ECC and modulation codes for 1-D and 2-D constraints.

CoordenaÃÃo de AperfeÃoamento de Pessoal de NÃvel Superior / This work presents a new structure for an all-digital BPSK demodulator developed for space communications that performs simultaneously the sampling and down-conversion of the the intermediate frequency signal to the baseband signal. The most important aspect of this work is the design of a new interpolator to retrieve lost samples during the down conversion process, and also to simplify the demodulator implementation. This interpolator correlates the samples of the output signal in such way that it was necessary to design a optimum filter appropriate to process the samples corrupted by gaussian and colored noise. The effects of the new interpolation at the noise are analyzed as well as the way it affects the whole demodulator performance. After performing the optimum filtering, the phase and symbol offsets are estimated and corrected. For the phase, for example, it was used a DPLL (Digital Phase Locked Loop), a digital variation of the PLL, a well known structure and largely utilized in analogical electronics. The DPLL is a closed-loop structure that estimates and corrects the values for the angular which corresponds to the phase deviation caused by the offset between the transmitter and receiver oscilators. For the timing parameter estimation, it was used the Oerder&Meyer estimator that is the digital equivalent to the well known square timing recovery structure. After that, the correction is performed by an interpolation operation over the samples of the received signal, where a filter, named Farrow filter, is applied to these samples, calculating the new samples of that signal at the corrected time instants. This system is mathematically described, all the signals expressions of every stage of the demodulator are analyzed, including the noise statistics. Some computational simulation results are shown and the performance degradation is discussed. / Este trabalho apresenta um modelo de demodulador que realiza simultaneamente a conversÃo analÃgico-digital e a conversÃo em frequÃncia por amostragem em banda passante de um sinal com modulaÃÃo BPSK (Binary Phase Shift Keying) para aplicaÃÃo em enlaces espaciais. O aspecto mais importante do trabalho foi o desenvolvimento de uma nova operaÃÃo de interpolaÃÃo para recuperaÃÃo das amostras perdidas na conversÃo de frequÃncia e que simplifica a implementaÃÃo do demodulador. O interpolador correlaciona as amostras do sinal de forma que torna-se necessÃrio o projeto de um filtro Ãtimo apropriado para processar as amostras corrompidas e mitigar os efeitos do ruÃdo gaussiano e colorido. Os efeitos deste novo interpolador no ruÃdo sÃo analisados, assim como a forma em que ele afeta a performance do sistema. ApÃs a filtragem Ãtima, segue a correÃÃo dos erros de sincronismo de atraso de simbolo e de fase. Para a recuperaÃÃo do sincronismo de fase foi utilizado um DPLL (Digital Phase Locked Loop), uma variante digital de uma estrutura bastante conhecida e utilizada em eletrÃnica analÃgica. O DPLL à uma estrutura em malha fechada que estima e corrige os valores do desvio angular das amostras, o que corresponde ao devio provocado pela diferenÃa de fase entre os osciladores do transmissor e do receptor. Para a recuperaÃÃo do atraso de sÃmbolo foi utilizada, para estimaÃÃo do tempo de atraso, o estimador de Oerder&Meyer que à o equivalente digital da conhecida recuperaÃÃo de temporizaÃÃo em tempo contÃnuo com a lei quadrÃtica. ApÃs a estimaÃÃo ser realizada, à feita a correÃÃo deste atraso nas amostras do sinal recebido atravÃs de uma operaÃÃo de interpolaÃÃo, onde novos valores do sinal sÃo calculados para os instantes de tempo corrigidos. Essa operaÃÃo à realizada por um filtro interpolador, uma estrutura especial conhecida como estrutura de Farrow. O sistema proposto foi descrito matematicamente, sendo analisadas as expressÃes dos sinais nos diferentes estÃgios do conversor, bem como as estatÃsticas dos sinais de ruÃdo. Apresentam-se os resultados da simulaÃÃo computacional nos quais se avalia a perda no desempenho do demodulador, analisando suas causas.

The master's thesis briefly analyses the principle of OFDM modulation, possibilities of the synchronization and channel estimation in OFDM. The simply model of OFDM system is made in MATLAB. Because of the implementation in FPGA is generated the behavioral description of the OFDM demodulator through the combination of the schematics description and the description in the VHDL language. The ISE development environment is used.

Thesis (MScEng (Electrical and Electronic Engineering))--University of Stellenbosch, 2010. / ENGLISH ABSTRACT: This thesis describes the design and implementation of a software based QPSK demodulator with a demodulation speed of 100 Mbps. The objective of the thesis was to identify a topology for the QPSK demodulator that would allow for high data rates and the design of the synchronization algorithms for carrier and symbol recovery. The QPSK demodulator was implemented on an Altera Stratix II field programmable gate array (FPGA), which does complex I and Q sampling on a down converted 720 MHz QPSK signal. The I and Q down converted baseband signals are sent through matched filters which are implemented with discrete components to maximize the signal to noise ratio of the received rectangular baseband pulses. A 1 GSPS direct digital synthesizer (DDS) is used to generate the synchronous clock for the analog to digital converters which samples the matched filter outputs. The demodulator uses two samples per symbol to demodulate the QPSK signal. A dual locking system is implemented to have a wide pre-locking filter for symbol synchronization and a narrow band post-lock filter to minimize the loop noise. A symbol lock detection algorithm decides when the symbol recovery loop is locked and switches between the loop filters. A second 1 GSPS DDS output is mixed with a local oscillator to generate the 1.44 GHz LO signal for the quadrature down conversion. The carrier recovery loop uses a numerically controlled oscillator inside the FPGA for initial carrier acquisition which allows for very wide locking bandwidth. After lock is achieved, the external carrier recovery loop takes over and removes any frequency offset in the complex baseband signal by changing the frequency of the DDS. A QPSK modulator was also developed to provide a QPSK signal with known data. The modulator can generate any constellation diagram up to 256 points. / AFRIKAANSE OPSOMMING: Hierdie tesis bespreek die ontwerp en implementasie van ’n sagteware gebaseerde QPSK demodulator met ’n demodulasie spoed van 100 Mbps. Die doelstelling is om ’n topologie te identifiseer vir ’n QPSK demodulator wat ’n hoë datatempo sal toelaat en ook om sinkronisasie algoritmes te ontwikkel vir draer en simbool herkenning. Die QPSK demodulator is geïmplimenteer op ’n Stratix II FPGA van Altera wat kompleks basisband monstering doen op infase en kwadratuur basisband seine. Die basisband seine word gegenereer van ’n 720 MHz QPSK sein met ’n kwadratuur menger wiese uittrees deur puls passende filters gestuur word om die sein tot ruis verhouding te maksimeer. ’n Een gigamonster per sekonde direk digitale sintetiseerder (DDS) is gebruik om die klok vir die analoog na digitaal omsetters te genereer vir sinkrone monstering van die pulse passende filter uittrees. Die demodulator gebruik twee monsters per simbool om ’n QPSK sein te demoduleer. ’n Tweevoudige sluit algoritme word gebruik vir die simbool sinkronisasie waar ’n wyeband filter die inisiële sluit funksie verrig en dan word daar oorgeslaan na ’n nouband filter vir fase volging wat die ruis in die terugvoerlus verminder. Daar is ’n simbool sluit detektor wat identifiseer wanneer die simbool beheerlus gesluit is en selekteer dan die gepaste filter. ’n Tweede DDS en ’n sintetiseerder se uittrees word gemeng om ’n 1.44 GHz draer te genereer vir kohurente frekwensie translasie in die kwadratuur menger. Die draer sinkronisasie gebruik ’n numeries beheerbare ossilator vir die inisiële frekwensie en fase sluit wat baie vinnig geimplenteer kan word omdat dit alles in sagteware binne in die FPGA gebeur. Na die interne draer beheerlus gesluit is, neem die eksterne beheerlus oor om enige fase of frekwensie afsette in die kompleks basisband seine van die kwadratuur menger te verwyder deur die frekwensie van die draer DDS te beheer. ’n QPSK modulator is ook ontwikkel om verwysings data te genereer. Enige konstelasie vorm tot 256 punte kan geimplementeer word.

<p>The society expects a global interconected digital communication system offering multimedia services, information on demand and interchange of information with a high data rates and low cost. </p><p>All this can not be realized with the terrestrial nets used nowadays cause it is necessary a high economic inversion to get a competitive capacity to interchange information between server and user. The next generation of satellite must have characteristics which improve the current generation, one important requirement is that the same satellite could make a treatment of the different input signals. With this we can avoid a spent of lots of money and time because we do not need terrestrial stations which modify the signals before the information is sent to the satellite.</p><p>For all this, we need an on board treatment of the information in the satellite. We design a frequency bank reallocation (FBR) network by using a filter bank system. This is the first step of the thesis. After we get FBR we introduce some different input signals and analyze the output, using parameters like symbol error rate and variance.</p><p>One important part in the thesis is the QAM signals used to test our system. For this, we design a modulator and a demodulator of QAM4, 16 and 64, paying more attention in the QAM64, cause is the modulation where more errors can appear due to we have got more possible chances which means more precision in the recovery of the signal.</p>

The society expects a global interconected digital communication system offering multimedia services, information on demand and interchange of information with a high data rates and low cost. All this can not be realized with the terrestrial nets used nowadays cause it is necessary a high economic inversion to get a competitive capacity to interchange information between server and user. The next generation of satellite must have characteristics which improve the current generation, one important requirement is that the same satellite could make a treatment of the different input signals. With this we can avoid a spent of lots of money and time because we do not need terrestrial stations which modify the signals before the information is sent to the satellite. For all this, we need an on board treatment of the information in the satellite. We design a frequency bank reallocation (FBR) network by using a filter bank system. This is the first step of the thesis. After we get FBR we introduce some different input signals and analyze the output, using parameters like symbol error rate and variance. One important part in the thesis is the QAM signals used to test our system. For this, we design a modulator and a demodulator of QAM4, 16 and 64, paying more attention in the QAM64, cause is the modulation where more errors can appear due to we have got more possible chances which means more precision in the recovery of the signal.

This dissertation presents system and circuit development of the low-power multi-gigabit CMOS demodulator using analog and mixed demodulation techniques. In addition, critical building blocks of the low-power analog quadrature front-ends are designed and implemented using 90 nm CMOS with a targeted compatibility to the traditional demodulator architecture. It exhibits an IF-to-baseband conversion gain of 25 dB with 1.8 GHz of baseband bandwidth and a dynamic range of 23 dB while consuming only 46 mW from a 1 V supply voltage. Several different demodulators using analog signal processor (ASP) are implemented: (1) an ultra-low power non-coherent ASK demodulator is measured to demodulate a maximum speed of 3 Gbps while consuming 32 mW from 1.8 V supply; (2) a mere addition of 7.5 mW to the aforementioned analog quadrature front-end enables a maximum speed of 2.5 Gbps non-coherent ASK demodulation with an improved minimum sensitivity of -38 dBm; (3) a robust coherent BPSK demodulator is shown to achieve a maximum speed of 3.5 Gbps based on the same analog quadrature front-end with only additional 7 mW. Furthermore, an innovative seamless handover mechanism between ASP and PLL is designed and implemented to improve the frequency acquisition time of the coherent BPSK demodulator. These demodulator designs have been proven to be feasible and are integrated in a 60 GHz wireless receiver. The system has been realized in a product prototype and used to stream HD video as well as transfer large multi-media files at multi-gigabit speed.

This project occupies with the creation modulated signal generator in MATLAB. There are explicit basic princips of modulation PSK, M-QAM, princip of system with spread spektrum and princip of access OFDM and MC-CDMA. Next there are explicit basic parametres and possibilities configuration of conversion analog PCI card CompuGen 4302, which serves as D/A convertor of signals created by PC.

This thesis describes design of Simulator FM-CW range finders. It is choosing the optimal method of realization and inform about basic properties of continuous working radar. The work includes an analysis of errors in real rangefinder and a numerical estimate of the maximum error in real devices. Contains detailed block diagram of simulator FM-CW range-finder and computer simulation of function generator frequency modulated signal, demodulator. Further work includes the complete construction documents for the preparation and implementation of basic functional verification

This work is dealing with the design of intermediate part of transmitter and reciever that use digital BPSK and QPSK modulations for microwave link that works in 24 – 26 GHz bands. Besides choosing the suitable modulator and demodulator there was need to provide proper connection of this part with transceiver Nortel CTR26-01M. Input and output of this intermediate part was take out to baseband, where was need to ensure the transfer of diferential inputs of modulator and demodulator to symetric leading for reason of data communication with PC, for which was created the algorithms to provide transmitting and receiving data. Complete structure controlled by the microcontroller has been enliven and furthemore there was created the measurement of chosen parameteres.