International Telemetering Conference Proceedings / October 25-28, 1999 / Riviera Hotel and Convention Center, Las Vegas, Nevada / L-3 Communications Telemetry & Instrumentation (L-3 T&I) has developed an advanced IBM PC-AT Telemetry, Tracking, and Commanding (TT&C) SATCOM system based on the utilization of Field Programmable Gate Array / Digital Signal Processing (FPGA/DSP) microprocessors. This system includes up-link, down-link, and range processing sections. Physically, the system consists of one IF Transceiver and two or more FPGA/DSP microprocessor boards called Advanced Processing Microprocessors (APMs). The form factor of these PWBs is compliant with full length, full height IBM PC PCI bus cards. This paper describes the features and functionality of an advanced Telemetry, Tracking, and Commanding Processing System (TT&CPS) based on the implementation of FPGA and DSP microprocessors. The high-level functional attributes of the TT&CPS are depicted in Figure 1. There are four main functional blocks: the IF Transceiver, the Down-Link Processing Section, the Up-Link Processing Section, and the Range Processor. The analog/IF circuitry in the IF Transceiver card interfaces between the 68–72 MHz (70 MHz, nominal) IF I/O signals and the Up-Link and Down-Link Processing Section's DSP equipment. The down-link portion of the IF Transceiver card has two user-selected input ports. From the selected input, the signal is processed through selectable bandwidth limiting, gain control, Doppler correction (optional), quadrature down-conversion to zero hertz (baseband), selectable baseband filtering, and precision Analog-to-Digital (A/D) conversion. The up-link portion of the IF Transceiver card takes I/Q digital data from the APM performing the up-link processing functions. This baseband I/Q digital data is Digital-to-Analog (D/A) converted, filtered, quadrature up-converted to 68–72 MHz, up-link Doppler corrected (optional), output level detected and level controlled, and sent to a two-position output selector switch. The down-link portion of the TT&CPS provides main carrier linear PM or BPSK or QPSK demodulation and can also, in composite linear PM demodulation mode, receive and demodulate FSK and/or BPSK subcarriers and ranging signals. The demodulators use symbol timing loops and bit decision circuits (matched filters) to perform the bit synchronization function. Several decoding algorithms, including differential, de-interleaving, Viterbi, and Reed-Solomon, are available for the down-link telemetry. Command format checking and CRC status is also available on FSK-demodulated data. Direct carrier BPSK/QPSK demodulation has decoding and frame synchronization capabilities. Because of the modular construction of the firmware and the use of FPGAs and DSPs, the system can be loaded with only the functions in use, lowering initial setup time while increasing overall system capability. To support a particular function, the card is downloaded with an “image,” which programs the FPGAs and DSPs at initialization. The user can change configurations by simply downloading a new set of instructions to the FPGA/DSP on the fly to keep the ground station running with minimal downtime. The flexibility of the design minimizes spare board costs, while achieving greater programmability at the end-user location.

The objective of the research is to develop high-speed ADCs and mixed-signal demodulator for multi-gigabit communication systems using millimeter-wave frequency bands in standard CMOS technology. With rapid advancements in semiconductor technologies, mobile communication devices have become more versatile, portable, and inexpensive over the last few decades. However, plagued by the short lifetime of batteries, low power consumption has become an extremely important specification in developing mobile communication devices. The ever-expanding demand of consumers to access and share information ubiquitously at faster speeds requires higher throughputs, increased signal-processing functionalities at lower power and lower costs. In today’s technology, high-speed signal processing and data converters are incorporated in almost all modern multi-gigabit communication systems. They are key enabling technologies for scalable digital design and implementation of baseband signal processors. Ultimately, the merits of a high performance mixed-signal receiver, such as data rate, sensitivity, signal dynamic range, bit-error rate, and power consumption, are directly related to the quality of the embedded ADCs. Therefore, this dissertation focuses on the analysis and design of high-speed ADCs and a novel broadband mixed-signal demodulator with a fully-integrated DSP composed of low-cost CMOS circuitry. The proposed system features a novel dual-mode solution to demodulate multi-gigabit BPSK and ASK signals. This approach reduces the resolution requirement of high-speed ADCs, while dramatically reducing its power consumption for multi-gigabit wireless communication systems.

As one of the major building blocks in a wireless receiver, the Analog-to-Digital Interface (ADI) provides link and transition between the analog Radio Frequency (RF) frontend and the baseband Digital Signal Processing (DSP) module. The rapid development of the radio technologies raises new design challenges for the receiver ADI implementation. Requirements, such as power consumption optimization, multi-standard compatibility, fast settling capability and wide signal bandwidth capacity, are often encountered in a low voltage ADI design environment. Previous research offers ADI design schemes that emphasize individual merit. A systematic ADI design methodology is, however, not suffciently studied. In this work, the ADI design for two receiver systems are employed as research vehicles to provide solutions for different ADI design issues. A zero-crossing demodulator ADI is designed in the 0.35µm CMOS technology for the Bluetooth receiver to provide fast settling. Architectural level modification improves the process variation and the Local Oscillation (LO) frequency offset immunity of the demodulator. A 16.2dB Signal-to-Noise Ratio (SNR) at 0.1% Bit Error Rate (BER) is achieved with less than 9mW power dissipation in the lab measurement. For ADI in the 802.11b/Bluetooth dual-mode receiver, a configurable time-interleaved pipeline Analog-to-Digital-Converter (ADC) structure is adopted to provide the required multi-standard compatibility. An online digital calibration scheme is also proposed to compensate process variation and mismatching. The prototype chip is fabricated in the 0.25µm BiCMOS technology. Experimentally, an SNR of 60dB and 64dB are obtained under the 802.11b and Bluetooth receiving modes, respectively. The power consumption of the ADI is 20.2mW under the 802.11b receiving mode and 14.8mW under the Bluetooth mode. In this dissertation, each step of the receiver ADI design procedure, from system level optimization to the transistor level implementation and lab measurement, is illustrated in detail. The observations are carefully studied to provide insight on receiver ADI design issues. The ADI design for the Ultra-Wide Band (UWB) receiver is also studied at system level. Potential ADI structure is proposed to satisfy the wide signal bandwidth and high speed requirement for future applications.

This work is aimed at an analysis of frequency demodulation, design, simulation, and construction of a coincidence demodulator. Chapter 1 explains the basic characteristics of frequency modulated (FM) signals and provides an overview of the required signal bandwidth, the signal spectrum, and the signal-to-noise ratio after demodulation. Chapter 2 describes each type of FM demodulator separately, and it includes all significant types of demodulator for FM radio broadcast. The function of the coincidence demodulator and its characteristics are explained in detail. Chapter 3 contains a theoretical solution of the phase shift network. Calculated values of the circuit elements are verified by simulation with a view to the total harmonic distortion of the demodulator output signal. Chapter 4 describes the front-end circuit of the receiver. Here, the filter design and the mixer circuit description are provided. The final part of the thesis presents the applicable laboratory task.

This work deals with evaluation of equipment used for non-contact measurement of distance between vehicles. First are discussed various principles of measuring and after the selection of the most appropriate solution is proposed a detailed block diagram of modulation, demodulation and evaluation of the whole system and its mathematical description. Another part is devoted to describing the activities of the microprocessor controller, with which is controlled evaluation part and to the control program. It also analyzes the maximal attainable accuracy of measurement and the errors that affect it. The last part includes a circuit design and simulation of selected functional block, which is a coincidence /quadrature/ detector and construction documents for evaluation and demodulation part of the measurement instrument.

This thesis is focused on a receiver for digital television broadcasting set-top box, mainly on its features, parameters and measurement. The important point of this work is the possibility to analyze and visualize the parallel transport stream in the same time and the solution of this problem. The principle of tuner and its measuring is deeply discussed. The text is supported with oscilloscope screenshots in particular parts of decoding stream. The set-top box is modified for laboratory measurement purpose and the transport stream output is added. An example laboratory exercise was created as a part of this work.

This thesis describes a design of a simulation of transmission of digital information via communication system and equalization of communication function. The layout of communication channel with multiway transmission is described in following part. Next part is about hardware modulator which generate modulated signal which is transmitted via communication channel and after is sampled by A/D convertion card to computer, where is equalizated and demodulated in Simulink. In the last part of this thesis, there is proposal of the laboratory task and its sample solution.

This master’s thesis is an introduction to the measurement of changes in tissue impedance of blood flow by impedance plethysmography. Other chapters deal with the kinds of plethysmographs and their principles. The aim is to draft four-electrode impedance plethysmograph to measure changes in tissue impedance depending on blood flow. First, describe the individual blocks of the medical instrument. The practical part of the master’s thesis involves circuit design four-electrode plethysmograph. Given that a very important role in its function plays a constant current source operating at a frequency of 60kHz, this subset was implemented and verified its correct function. To draw component schemes used program EAGLE version 5.10.0.