This thesis includes two topics. The first topic is a 868/915 MHz band ZigBee physical layer design. The second topic is a synchroniza- -tion design of DVB-T demodulators. The first topic includes simulations and a hardware design. This chip is a physical layer design for IEEE Std 802.15.4 standard applications, including both a transmitter and a receiver for 868/915 MHz band. The measurement of the maximum power is about 144 µW at 2.4 MHz. This chip is proved to be compliant with a low power consumption requirement. The second topic mainly includes an introduction of the DVZB-T transmitter, equivalent channel model, a demodulation design of the receiver and simulations. The algorithms of the receiver include symbol timing synchronization, frequency offset estimation and its compensation and scattered pilots synchronization.

International Telemetering Conference Proceedings / October 25-28, 1999 / Riviera Hotel and Convention Center, Las Vegas, Nevada / Three different demodulators applicable to the coherent demodulation of binary Gaussian Minimum Shift Keying (GMSK) signal are described and their performance compared. These include a near-optimal trellis demodulator, which utilizes two matched filters and Viterbi algorithm to carry out maximum likelihood sequence estimation, and a singlefilter threshold demodulator with and without pulse equalization. The performance of these demodulators in noise and adjacent channel interference (ACI) are compared for several signal BT products. The equalized threshold demodulator is shown to perform nearly as well as the near-optimal trellis demodulator in additive white Gaussian noise (AWGN), and substantially outperform the trellis demodulator under severe ACI condition.

This thesis proposes a multi-parameter implantable micro-stimulator system. By using wireless communication and the muli-parameter control, the infection caused by the wound could be avoided and various stimulation waveforms could be generated for different bio-medical applications. Besides, a graphic user interface (GUI) is implemented for the proposed micro-stimulator for the convenience of usage. Moreover, the in vitro experiments are carried out, where the neurons could be stimulated successfully. To reduce the system area caused by external capacitors required by traditional ASK demodulators, a C-less ASK demodulator is proposed in this thesis. A bias-based envelope detector and a Schmitt trigger are used for demodulation. Moreover, by enlarging the noise margin of the envelope detector, an all-MOS ASK demodulator is carried out such that no passive element is needed and the system area could be further reduced. Besides, two high sensitivity voltage-to-frequency (VFC) are proposed for the full duplex transmission. By using a voltage-to-current converter, a charge and discharge circuit, and an all-MOS voltage window comparator 1 (VWC1), a high sensitivity VFC1 is accomplished. Moreover, a linear VFC2 is also proposed by including a fast all-MOS voltage window comparator, VWC2. Finally, a wide range I/O buffer is proposed for the interface of the implantable micro-stimulator system. With the stacked PMOS and NMOS output stage and the dynamic gate bias generator, high voltage and low voltage signals (VDDH and VDDL) could be transmitted and received without any gate-oxide overstress and leakage currents.

International Telemetering Conference Proceedings / October 23-26, 2000 / Town & Country Hotel and Conference Center, San Diego, California / The Advanced Range Telemetry (ARTM) program is a tri-service telemetry modernization project whose goal is to assure that all Department of Defense (DoD) test and training ranges are able to use telemetry as necessary to carry out their respective missions. Multi-h Continuous Phase Modulation (CPM) has been selected by the ARTM JPO as the Tier II ARTM waveform, because it offers significant improvements over both legacy telemetry waveforms (PCM/FM) and the newly-introduced Tier I waveform (Feher-patented FQPSK) in terms of spectral containment and detection efficiency, while retaining a constant envelope characteristic. The paper describes the theoretical and measured performance of the ARTM Tier II multi-h CPM waveform, and the implementation of the trellis demodulator being developed for it.

Master of Science / Department of Electrical and Computer Engineering / Dwight D. Day / Low-power systems implemented on Field Programmable Gate Arrays (FPGA) have become more practical with advancements leading to decreases in FPGA power consumption, physical size, and cost. In systems that may need to operate for an extended time independent of a central power source, low-power FPGA’s are now a reasonable option. Combined with research into energy harvesting solutions, a FPGA-based system could operate independently indefinitely and be cost effective. Four simple demodulator designs were implemented on a FPGA to test and compare the performance and power consumption of each. The demodulators were a Counter that tracked the length of the input signal period, a One-Shot that counted the input edges over time, a Phase-Frequency Detector (PFD), and a PFD with preprocessing on the input signal to mitigate distortion introduces by the 1-bit subsampling. The designs demodulated a binary frequency shift keying (BFSK) signal using 10.69MHz and 10.71MHz as the input frequencies and a 1kHz data rate. The signal was 1-bit subsampled at 75kHz to provide the demodulators with a signal containing 15kHz and 35kHz. The design size, power consumption, and error performance of each demodulator were compared. At the frequencies and data rate used, the Counter and One-Shot are the most energy efficient by a significant margin over the PFDs. The error performance was nearly equal for all four. As the BFSK baseband frequencies and especially the data rate are increased, the PFD options are expected to be the better options as the Counter and One-Shot may not react quickly enough.

This thesis provides analysis and modeling for one of the Micro-Eletro-Mechanical System (MEMS) electrostatic actuator that consists of a micro-plate at the end of a cantilever beam, and introduces different type of MEMS electrostatic actuator; a paddle structure, which is a micro-plate suspended by two cantilever beams on each side. An electrode plate is placed right under the micro-plate to apply an actuation voltage. A step-by-step analysis explains how to obtain each parameter used for the simulations. Static and dynamic models are presented with governing equations for the paddle-shaped MEMS electrostatic actuator. The key findings are that the proposed electrostatic MEMS demodulator architecture taking advantage of the resonance circuit principle not only theoretically work in analytical model, and numerical simulations, but also work in real life. For the Amplitude Modulations (AM) demodulations, simulations with various damping factors are provided, and experimental data are discussed. By measuring the displacement using the phase detector circuit and vibrometer, as a proof of versatility of the demodulation architecture based on the MEMS electrostatic actuator, the results from Frequency Modulations (FM), Amplitude Shift Keying (ASK), and Frequency Shift Keying (FSK) demodulation scheme experiments that are conducted with the physically identical dimensions and configuration are provided. The future plan for further analysis and experiment is discussed at the end.

The first topic of this thesis is a C-less and R-less ASK (Amplitude Shift Keying) demodulator design for wireless implantable devices. Lots of prior ASK demodulators were composed of one or more capacitors which might be integrated in a chip or positioned off-chip on a PCB (Printed Circuit Board). The capacitor increases the area of the implantable system regardless of on-chip or off-chip, which violates the small-scale requirement for implanted applications. Thus, this work proposes a miniature ASK demodulator without any passive elements, i.e., R or C. The noise margin of the envelope detector in the C-less ASK demodulator is enlarged such that any Schmitt trigger or current limiting resistor is no longer needed. It results in the number of transistors required for the ASK demodulator circuit is reduced to 12. The second topic of this thesis is a design of a low-power 2-dimensional bypassing multiplier. The proposed bypassing cells constituting the multiplier skip redundant signal transitions when the horizontally (row) partial product or the vertically (column) operand is zero. Thorough post-layout simulations show that the power dissipation of the proposed design is reduced by more than 41% compared to the prior design with obscure penalty of delay and area.

This thesis provides analysis and modeling for one of the Micro-Eletro-Mechanical System (MEMS) electrostatic actuator that consists of a micro-plate at the end of a cantilever beam, and introduces different type of MEMS electrostatic actuator; a paddle structure, which is a micro-plate suspended by two cantilever beams on each side. An electrode plate is placed right under the micro-plate to apply an actuation voltage. A step-by-step analysis explains how to obtain each parameter used for the simulations. Static and dynamic models are presented with governing equations for the paddle-shaped MEMS electrostatic actuator. The key findings are that the proposed electrostatic MEMS demodulator architecture taking advantage of the resonance circuit principle not only theoretically work in analytical model, and numerical simulations, but also work in real life. For the Amplitude Modulations (AM) demodulations, simulations with various damping factors are provided, and experimental data are discussed. By measuring the displacement using the phase detector circuit and vibrometer, as a proof of versatility of the demodulation architecture based on the MEMS electrostatic actuator, the results from Frequency Modulations (FM), Amplitude Shift Keying (ASK), and Frequency Shift Keying (FSK) demodulation scheme experiments that are conducted with the physically identical dimensions and configuration are provided. The future plan for further analysis and experiment is discussed at the end.

<p> This thesis is principally concerned with the performance of the phase-locked FM demodulator under conditions of interference in comparison to the conventional FM demodulator. The linear no interference performance of the phase-locked oscillator is well known, however this aspect is included in the interests of completeness and reference.</p> <p> Mechanisms tor threshold effects in the phase-locked and conventional FM demodulator are discussed and compared. It is shown theoretically and experimentally that the noise threshold is reduced in the phase-locked FM demodulator by virtue of the limits of Ψi (t) being restricted by the noise bandwidth of' the feedback loop. Fall off in baseband signal level in the presence of noise was seen to be a function of θ(t) and (S/N)IF.</p> / Thesis / Master of Engineering (MEngr)

The proposed demodulator is an all-digital implementation of a FM demodulator. The proposed design intends to implement a FM demodulator for high-speed applications, which makes the requirements for analog components minimal. The proposed circuit is an all-digital quadrature demodulator, where the individual components have been implemented without using any multipliers. The topology uses a Pulse width modulation (PWM) block to avoid the need for a DAC. The Xilinx virtex-7 FPGA has been used as the reference device for the work. The circuit is validated through behavioral simulations and the results conclude the proposed circuit demodulates the targeted FM channel and provides the spectrum information for the targeted FM channel / Master of Science / With the rise in popularity of reconfigurable hardware, such as FPGAs, digital signal processing has become one of the most widespread usage of such devices. The major advantage of using FPGAs for implementing signal processing algorithms is that they provide very less time to market and can be re-modeled or modified in easily. Moreover, the netlists designed for FPGAs can be easily translated to ASICs. As wireless communication has become omnipresent, modulation and demodulation schemes have become an area of great interest. With the increase in data rates for the modern-day communication systems, the digital implementation of these algorithms is becoming more and more common. This is further aided by the advancements in high-speed ADCs and the Electronic Design Automation (EDA) tools, which have made the usage of FPGAs lot more feasible and a lot more efficient. This work discusses the demodulation scheme for one of the most widespread modulation algorithms, Frequency Modulation (FM). An all-digital FM demodulator design is proposed for highspeed implementation on FPGAs. The proposed design is an all-digital quadrature I-Q based demodulator.