No description available.

This work presents modeling and analysis techniques for low-profile transformers in power electronics. Based on the modeling and analysis, the design methodologies and design tools are provided. High frequency low-profile transformer 1-D winding loss, core loss and temperature rise models are derived in terms of the transformer geometry parameters. A 2-D FEA (Finite Element Analysis) is used to visualize the high frequency electromagnetic field and current density distribution, and to quantify high frequency power dissipation and energy storage in transformer by taking the skin effect, proximity effect, and edge effect into account. The characteristics of winding arrangements (interleaved or sandwiched, balanced or unbalanced) with different types of wire (solid wire, Litz wire, and printed wire) are accurately predicted. An algorithm is developed to design a low-profile transformer that has a maximum power density and meets a given set of specifications. The maximum achievable power density for a given power level and output voltage is computed based on only one fundamental constraint: temperature rise. A nonlinear optimization programming tool is developed based on the algorithm. Consequently, the maximum achievable power density and the required number of turns are determined, along with the optimum operating frequency and core geometry. / Ph. D.

This thesis outlines the notion of '<i>Disruptive Futuring'</i> as a new design methodology to addressing climate change. It is founded on making a connection between our behaviour as individuals and the environment. Since the publishing of 'Our Common Future' (Brundtland Commission.1987) major bodies have been publicly documenting the damage that climate change is having on the planet. This has been followed by the creation of United Nations Climate Change Conference international incentives including the Kyoto Protocol and national attempts including government departments and NGO projects. All have been directed to address the issue of climate change but have seen minimal success. Psychology plays a significant role in understanding and promoting human behavioural change and how we prioritise particular decisions or actions. However, until recently it has carried less weight in a design approach to solving behavioural problems in climate change. The primary issue is that climate change isn't a normal behavioural problem, and numerous psychologists including Stoknes (2015) highlight its incompatibility with innate human motivation. Newly explored areas within psychology and behavioural economics expose some of the reasons we may react to climate change with lower importance then other less damaging problems. <i>Disruptive Futuring</i> provides a new methodology based on thinkers such as Fogg (2002), Gilbert (2015), Dubner and Levitt. (2009), Marshall(2014), Pink(2009) and Stoknes (2015) to improve quantitative and qualitative adoption of designed interventions aimed at changing behaviours in order to accelerate human actions affecting climate change. This thesis takes a research through design approach that incorporates reflective practice. The research builds upon a literature review evaluating our connection with climate change, resulting in combining behavioural psychology with mapping and lens methods. <i>Disruptive Futuring</i> is presented as anew design methodology that develops new types of behavioural change using what Thaler & Sunstein (2009) describe as "Nudge" as a process to reroute people to new actions and flows in their everyday lives. These behavioural changes are achieved through framing climate change in ways humans are motivated by. Three practice-based projects pilot the methodology of <i>Disruptive Futuring</i> by exploring the topics of energy, water and food. These areas were selected because of their significance to our physiological requirements as highlighted by Maslow (1943). The projects result in three systems-based interventions aimed at changing behaviours that negatively impact climate change. It is observed through reflection that this methodology provides a context for designers to work in an oblique way; it has a preference to influence thinking and designing in systems; and that complex psychological concepts can be applied through designed interventions that reduce the conflict between our psychological composition and the human perception of climate change. This research explores the capability and capacity for <i>Disruptive Futuring </i>to bring climate change psychology into a unified way for designers to use during the conception and research stages of designing interventions, technology or services that target behavioural change, decisions making and create new ways of living to have less impact on climate change.

No description available.

In this work, the formulation and the implementation of innovative methodological paradigms for the design of unconventional array architectures for future generation communication systems has been addressed. By exploiting the potentialities of the codesign strategy for elementary radiators in an irregularly clustered array architectures and by introducing an innovative capacity-driven design paradigm, the proposed methodologies allow to effectively design unconventional array architectures with optimal trade-offs in terms of performance and complexity/costs. The codesign synthesis strategy is proposed to solve the arising massive multi-objective design problem aimed at fitting the multiple objectives and requirements on the "free-space" performance of the array architecture. Afterward, the capacity-driven design paradigm is formulated and implemented for the design of MIMO array architectures to maximize the quality of the communication system in first place instead of considering "free-space" figures-of-merit. A set of numerical results has been provided (i) to validate the proposed paradigms in real-application scenarios and (ii) to provide insights on the effectiveness, the limitations and the potentialities of proposed design methodologies.

Uma das maiores restrições que existe atualmente no fluxo de projeto de CIs é a necessidade de um ciclo menor de desenvolvimento. Devido às grandes dimensões dos sistemas atuais, é muito provável encontrar no projeto de blocos IP, erros ou bugs originados na passagem de uma dada especificação inicial para seus correspondentes modelos de descrição de hardware. Isto faz com que seja necessário verificar tais modelos para garantir aplicações cem por cento funcionais. Uma das técnicas de verificação que tem adquirido bastante popularidade recentemente é a verificação funcional, uma vez que é uma alternativa que ajuda a manter baixos custos de validação dos modelos HDL ao longo do projeto completo do circuito. Na verificação funcional, que está baseada em ambientes de simulação, a funcionalidade completa (ou relevante) do modelo é explorada, aplicando-se casos de teste, um após o outro. Isto permite examinar o modelo em todas as seqüências e combinações de entradas desejadas. Na verificação funcional, existe a possibilidade de simular o modelo estimulando-o com casos de teste aleatórios, o qual ajuda a cobrir um amplo número de estados. Para facilitar a aplicação de estímulos em simulação de circuitos, é comum que espaços definidos por parâmetros de entrada sejam limitados em sua abrangência e agrupados de tal forma que subespaços sejam formados. No desenvolvimento de testbenches, os geradores de estímulos aleatórios podem ser criados de forma a conter subespaços que se sobrepõem (resultando em estímulos redundantes) ou subespaços que contenham condições que não sejam de interesse (resultando em estímulos inválidos). É possível eliminar ou diminuir, os casos de teste redundantes e inválidos através da aplicação de metodologias de modificação do espaço de estímulos de entrada, e assim, diminuir o tempo requerido para completar a simulação de modelos HDL. No presente trabalho, é realizada uma análise da aplicação da técnica de organização do espaço de entrada através de domínios de parâmetros do IP, e uma metodologia é desenvolvida para tal, incluindo-se, aí, uma ferramenta de codificação automática de geradores de estímulos aleatórios em linguagem SyatemC: o GET_PRG. Resultados com a aplicação da metodologia é comparada a casos de aplicação de estímulos aleatórios gerados a partir de um espaço de estímulos de entrada sem modificações.Como esperado, o número de casos de teste redundantes e inválidos aplicados aos testbenches foi sempre maior para o caso de estimulação aleatória a partir do espaço de estímulos de entrada completo com um tempo de execução mais longo. / One of the strongest restrictions that exist throughout ICs design flow is the need for shorter development cycles. This, along with the constant demand for more functionalities, has been the main cause for the appearance of the so-called System-on-Chip (SOC) architectures, consisting of systems that contain dozens of reusable hardware blocks (Intellectual Properties, or IPs). The increasing complexity makes it necessary to thoroughly verify such models in order to guarantee 100% functional applications. Among the current verification techniques, functional verification has received important attention, since it represents an alternative that keeps HDL validation costs low throughout the circuits design cycle. Functional verification is based in testbenches, and it works by exploring the whole (or relevant) models functionality, applying test cases in a sequential fashion. This allows the testing of the model in all desired input sequences and combinations. There are different techniques concerning testbench design, being the random stimulation an important approach, by which a huge number of test cases can be automatically created. In order to ease the stimuli application in circuit simulation, it is common to limit the range of the space defined by input parameters and to group such restricted parameters in sub-spaces. In testbench development, it may occur the creation of random stimuli generators containing overlapping sub-spaces (resulting in redundant stimuli) or sub-spaces containing conditions of no interest (resulting in invalid stimuli). It is possible to eliminate, or at least reduce redundant and invalid test cases by modifying the input stimuli space, thus, diminishing the time required to complete the HDL models simulation. In this work, the application of a technique aimed to organize the input stimuli space, by means of IP parameter domains, is analyzed. A verification methodology based on that is developed, including a tool for automatic coding of random stimuli generators using SystemC: GET_PRG. Results on applying such a methodology are compared to cases where test vectors from the complete verification space are generated. As expected, the number of redundant test cases applied to the testbenches was always greater for the case of random stimulation on the whole (unreduced, unorganized) input stimuli space, with a larger testbench execution time.

Este trabalho aborda a gestão do desenvolvimento de produtos e a inovação tecnológica, amplamente aceitos como um meio de assegurar sobrevivência aos negócios. Realizou-se uma revisão bibliográfica identificando os diferentes fatores que os influenciam. Descreve-se uma pesquisa, aplicada em 2004, que avaliou as metodologias de desenvolvimento de produtos utilizadas em pequenas e médias empresas industriais (PME\'s), em uma região específica do estado de São Paulo, pertencentes ao setor metal-mecânico da economia brasileira e que adotou como instrumento de coleta de dados um questionário, dividido por assuntos, projetado e aplicado em entrevistas presenciais em uma amostra de 32 empresas. Este trabalho propõe e ordena um conjunto de diretrizes de apoio ao esforço de inovação tecnológica em PME\'s industriais, evidenciadas em uma ferramenta para o diagnóstico do estágio de amadurecimento, que se fundamentada na categorização das empresas pesquisadas, segundo os fatores de inovação tecnológica abordados por diversos autores. O método foi validado pela análise da implantação de diretrizes, em épocas distintas, em três empresas participantes da pesquisa. / This work approaches the product development management and technological innovation, widely seen as way of ensuring business survival. It was held a bibliographic review about the different factors that influence them. The work reports a research, applied in 2004, that evaluated product development methodologies used on industrial small and medium enterprises (SME\'s), in a specific region on the state of Sao Paulo. All of these SME\'s belong to the metal-mechanics sector of the Brazilian economy. The research adopted a questionnaire as an instrument for data collection. This questionnaire was divided in subjects, and was developed and applied in personal meetings in a sample of 32 enterprises. This work propounds and orders a support guidelines to the effort of technological innovation in industrial SME\'s, evidenced in a tool for the diagnosis of the mature degree, based on the classification of the studied companies, according to factors of technological innovation from the approach of different authors. The method was validated by the analysis of the guidelines implantation, at distinct periods of time, in three participant companies of the research.

Uma das maiores restrições que existe atualmente no fluxo de projeto de CIs é a necessidade de um ciclo menor de desenvolvimento. Devido às grandes dimensões dos sistemas atuais, é muito provável encontrar no projeto de blocos IP, erros ou bugs originados na passagem de uma dada especificação inicial para seus correspondentes modelos de descrição de hardware. Isto faz com que seja necessário verificar tais modelos para garantir aplicações cem por cento funcionais. Uma das técnicas de verificação que tem adquirido bastante popularidade recentemente é a verificação funcional, uma vez que é uma alternativa que ajuda a manter baixos custos de validação dos modelos HDL ao longo do projeto completo do circuito. Na verificação funcional, que está baseada em ambientes de simulação, a funcionalidade completa (ou relevante) do modelo é explorada, aplicando-se casos de teste, um após o outro. Isto permite examinar o modelo em todas as seqüências e combinações de entradas desejadas. Na verificação funcional, existe a possibilidade de simular o modelo estimulando-o com casos de teste aleatórios, o qual ajuda a cobrir um amplo número de estados. Para facilitar a aplicação de estímulos em simulação de circuitos, é comum que espaços definidos por parâmetros de entrada sejam limitados em sua abrangência e agrupados de tal forma que subespaços sejam formados. No desenvolvimento de testbenches, os geradores de estímulos aleatórios podem ser criados de forma a conter subespaços que se sobrepõem (resultando em estímulos redundantes) ou subespaços que contenham condições que não sejam de interesse (resultando em estímulos inválidos). É possível eliminar ou diminuir, os casos de teste redundantes e inválidos através da aplicação de metodologias de modificação do espaço de estímulos de entrada, e assim, diminuir o tempo requerido para completar a simulação de modelos HDL. No presente trabalho, é realizada uma análise da aplicação da técnica de organização do espaço de entrada através de domínios de parâmetros do IP, e uma metodologia é desenvolvida para tal, incluindo-se, aí, uma ferramenta de codificação automática de geradores de estímulos aleatórios em linguagem SyatemC: o GET_PRG. Resultados com a aplicação da metodologia é comparada a casos de aplicação de estímulos aleatórios gerados a partir de um espaço de estímulos de entrada sem modificações.Como esperado, o número de casos de teste redundantes e inválidos aplicados aos testbenches foi sempre maior para o caso de estimulação aleatória a partir do espaço de estímulos de entrada completo com um tempo de execução mais longo. / One of the strongest restrictions that exist throughout ICs design flow is the need for shorter development cycles. This, along with the constant demand for more functionalities, has been the main cause for the appearance of the so-called System-on-Chip (SOC) architectures, consisting of systems that contain dozens of reusable hardware blocks (Intellectual Properties, or IPs). The increasing complexity makes it necessary to thoroughly verify such models in order to guarantee 100% functional applications. Among the current verification techniques, functional verification has received important attention, since it represents an alternative that keeps HDL validation costs low throughout the circuits design cycle. Functional verification is based in testbenches, and it works by exploring the whole (or relevant) models functionality, applying test cases in a sequential fashion. This allows the testing of the model in all desired input sequences and combinations. There are different techniques concerning testbench design, being the random stimulation an important approach, by which a huge number of test cases can be automatically created. In order to ease the stimuli application in circuit simulation, it is common to limit the range of the space defined by input parameters and to group such restricted parameters in sub-spaces. In testbench development, it may occur the creation of random stimuli generators containing overlapping sub-spaces (resulting in redundant stimuli) or sub-spaces containing conditions of no interest (resulting in invalid stimuli). It is possible to eliminate, or at least reduce redundant and invalid test cases by modifying the input stimuli space, thus, diminishing the time required to complete the HDL models simulation. In this work, the application of a technique aimed to organize the input stimuli space, by means of IP parameter domains, is analyzed. A verification methodology based on that is developed, including a tool for automatic coding of random stimuli generators using SystemC: GET_PRG. Results on applying such a methodology are compared to cases where test vectors from the complete verification space are generated. As expected, the number of redundant test cases applied to the testbenches was always greater for the case of random stimulation on the whole (unreduced, unorganized) input stimuli space, with a larger testbench execution time.

Este trabalho propõe uma metodologia de projeto para fabricação ou Design Methodology for Manufacturing (DFM) utilizando a Programação Geométrica (PG) e os métodos tipo Newton para resolver problemas de otimização não-linear, os quais definem e assistem o projeto de circuitos analógicos. Depois, essa metodologia é aplicada e validada através do projeto de uma fonte de referência. Nos últimos anos, a tendência do aumento na densidade de transistores previsto pela lei de Moore tornou o problema do projeto dos circuitos dimensionalmente mais complexo. Além disso, uma maior densidade de transistores implica na diminuição das dimensões características do processo tornando-o mais sensível às variações de processo e as condições ambientais. As diferenças apresentadas entre o circuito projetado e aquele testado dão evidências de perdas de rendimento, as quais são atribuídas numa grande proporção ao processo de projeto. Devido à grande responsabilidade que o projetista tem neste problema, o projeto analógico deve ser focado para novas abordagens que levem em conta o desempenho e o rendimento conjuntamente. Em primeiro lugar, a metodologia proposta obtém um ponto inicial com um conjunto de especificações de desempenho adequadas, o qual vai ser usado na análise do impacto que tem o mismatch e as variações de processo sobre as especificações. Uma vez que o comportamento estatístico e determinístico do circuito foi caracterizado, uma nova estratégia de melhoria de rendimento foi implementada usando PG. A intenção de obter um projeto com um conjunto de especificações de bom desempenho envolve diretamente o rendimento do circuito, pois um conjunto de especificações ótimo obtido através da estrutura típica da PG não garante a obtenção de um projeto comercial e competitivo. Assim, este trabalho estabelece um método de projeto que combina a facilidade na obtenção do ótimo global da Programação Geométrica com uma nova análise de mismatch e de pior caso a qual permitiu uma redução nos tempos de computação mantendo semelhantes os valores de desempenho nominais. Usando a metodologia de projeto para fabricação proposta neste trabalho foi obtido um projeto de uma fonte de referência com um rendimento maior que 37% comparado com uma estratégia de projeto típica, sem nenhuma penalização significativa nas especificações de desempenho. / This work proposed a Design Methodology for Manufacturing (DFM) using Geometric Programming (GP) and Newton-like methods to solve non-linear optimization problems, which define and aid the design of analog circuits. Afterwards, this methodology is applied and validated through the design of a voltage reference circuit. Over the last years, the tendency of the increasing on the transistor density predicted by the Moore Law has turned the circuit design problem dimensionally more complex. Additionally, a higher transistor density implies shrinkage on the feature dimensions of the process making it more sensitive to the process variations and environmental conditions. The differences between the designed circuit and the tested one give an evidence of yield losses, which are attributed in a great proportion to the design process. Due to the high responsibility of the designer on this problem, the analog design must be focused on new approaches that jointly manage performance and yield. In first place, the proposed methodology obtain a initial point with a suitable set of performance specifications, which will be used to analyze the impact of the mismatch and process variation over the design specifications. Once the statistical and deterministic behavior of the circuit was characterized, a new yield improvement strategy is implemented using Geometric Programming. Attempting to obtain a design with a set of high performance specifications directly involves the circuit yield, because an optimal performance set obtained by the traditional framework of GP does not assure the obtaining of a marketable and competitive design. So, this works establish a design method that combine the advantage of obtaining global optimum in Geometric Programming with a new mismatch and worst-case analysis that enabled a reduction in their computation time and maintain the initial nominal performance values. Using the design methodology for manufacturing proposed in this work, a voltage reference design with 37% better yield than one obtained with a typical design strategy without any significant penalty on their performance specs was achieved.

One of the main challenges posed by 4G wireless communication systems is achieving flexible, programmable multi-standard radio transceivers with maximum hardware share amongst different standards at a minimum power consumption. Evaluating the feasibility and performance of different multi-standard/multi-band radio solutions at an early stage, i.e. system level, is key for succeeding in surmounting this challenge. This entails for- mulation of the transceiver budget for several RF architectures and frequency plans with different degrees of hardware sharing. This task is complicated by the fact that transceiver blocks can have different implementations that lead to different performances. The tools that are available for use at present have only analysis capabilities or address only one standard and/or receiver architecture at a time.In the belief that a new approach to this problem is necessary, the work that has led to this thesis proposes a novel methodology that automates the design-space explo- ration of integrated multi-standard wireless radio receivers. This methodology has been implemented in a multi-standard RF Transceiver Architecture Comparison Tool, TACT. TACT helps surmounting many of the challenges faced by RF system designers targeting multi-standard/multi-band radio receivers.The goal of the algorithms TACT is built upon is to find a multi-standard receiver frequency plan and budget that meets or exceeds the specifications of the addressed wire- less standards while keeping the requirements of each of the receiver blocks as relaxed as possible. TACT offers RF engineers a deep insight into the receiver behavior at a very early stage of the design flow. It models the impact of critical circuit non-idealities using a high level of abstraction. This reduces the number of design iterations and, thus, the time-to-market of the solution. The reuse of already available intellectual property (IP) blocks is also considered in TACT, what can result in a significant cost reduction of the receiver implementation. A combination of a behavioural-based cooperative multi-agent optimization and deterministic techniques is proposed.The capabilities of the proposed techniques and developed tool are illustrated through case studies addressing different design challenges the design of multi-standard receivers present.The last part of this thesis is devoted to one of the key blocks of any communica- tions receiver: the analog-to-digital converter. This work focuses on modeling and design methodologies for continuous-time ΔΣ modulators. A method to evaluate the stability margin of continuous-time ΔΣ modulators as a function of the timing uncertainty effects is proposed. / QC 20100907 / RaMSiS