A complexidade no projeto de sistemas eletrônicos tem aumentado devido à evolução tecnológica e permite a concepção de sistemas inteiros em um único chip (SoCs – do inglês, Systems-on-Chip). Com o objetivo de reduzir a alta complexidade de projeto, custos de projeto e o tempo de lançamento do produto no mercado, os sistemas são desenvolvidos em módulos funcionais, pré-verificados e pré-projetados, denominados de núcleos de propriedade intelectual (IP – do inglês, Intellectual Property). Esses núcleos IP podem ser reutilizados de outros projetos ou adquiridos de terceiros. Entretanto, é necessário prover uma estrutura de comunicação para interligar esses núcleos e as estruturas atuais (barramentos) são inadequadas para atender as necessidades dos futuros SoCs (compartilhamento de banda, falta de escalabilidade). As redes-em-chip (NoCs{ XE "NoCs" } – do inglês, Networks-on-Chip) vêm sendo apresentadas como uma solução para atender essas restrições. No desenvolvimento de sistemas embarcados baseados em redes-em-chip, deve-se personalizar a rede para atendimento de restrições. Essa exploração de espaço de projeto (EEP), segundo uma infinidade de trabalhos, é realizada em tempo de projeto, supondo-se que é conhecido o perfil das aplicações que devem ser executadas pelo sistema. No entanto, cada vez mais sistemas embarcados aproximam-se de dispositivos genéricos de processamento (como palmtops), onde as tarefas a serem executadas não são inteiramente conhecidas a priori. Com a mudança dinâmica da carga de trabalho de um sistema embarcado, a busca pelo atendimento de requisitos pode então ser enfrentada por mecanismos adaptativos, que implementam dinamicamente a EEP. No âmbito deste trabalho, a EEP em tempo de execução provê mecanismos adaptativos que deverão realizar suas funções para atendimento de restrições de projeto. Consequentemente, EEP em tempo de execução pode permitir resultados ainda melhores, no que diz respeito a sistemas embarcados com restrições de projetos rígidas. É possível maximizar o tempo de duração da energia da bateria que alimenta um sistema embarcado ou, até mesmo, diminuir a taxa de perda de deadlines em um sistema de tempo real soft, realocando em tempo de execução tarefas de modo a gerar menor taxa de comunicação entre os processadores, desde que o sistema seja executado em um tempo suficiente para amortizar os custos de migração. Neste trabalho, foi utilizada a combinação de heurísticas de alocação da área dos Sistemas Computacionais Distribuídos como, por exemplo, algoritmos bin-packing e linear clustering. Resultados mostraram que a realocação de tarefas, utilizando uma combinação Worst-Fit e Linear Clustering, reduziu o consumo de energia e a taxa de perda de deadlines em 17% e 37%, respectivamente, utilizando o modelo de migração por cópia. / The complexity of electronic systems design has been increasing due to the technological evolution, which now allows the inclusion of a complete system on a single chip (SoC – System-on-Chip). In order to cope with the corresponding design complexity and reduce design costs and time-to-market, systems are built by assembling pre-designed and pre-verificated functional modules, called IP (Intellectual Property) cores. IP cores can be reused from previous designs or acquired from third-party vendors. However, an adequate communication architecture is required to interconnect these IP cores. Current communication architectures (busses) are unsuitable for the communication requirements of future SoCs (sharing of bandwidth, lack of scalability). Networks-on-Chip (NoC) arise as one of the solutions to fulfill these requirements. While developing NoC-based embedded systems, the NoC customization is mandatory to fulfill design constraints. This design space exploration (DSE), according to most approaches in the literature, is achieved at compile-time (off-line DSE), assuming the profiles of the tasks that will be executed in the embedded system are known a priori. However, nowadays, embedded systems are becoming more and more similar to generic processing devices (such as palmtops), where the tasks to be executed are not completely known a priori. Due to the dynamic modification of the workload of the embedded system, the fulfillment of requirements can be accomplished by using adaptive mechanisms that implement dynamically the DSE (run-time DSE or on-line DSE). In the scope of this work, DSE is on-line. In other words, when the system is running, adaptive mechanisms will be executed to fulfill the requirements of the system. Consequently, on-line DSE can achieve better results than off-line DSE alone, especially considering embedded systems with tight constraints. It is thus possible to maximize the lifetime of the battery that feeds an embedded system, or even to decrease the deadline miss ratio in a soft real-time system, for example by relocating tasks dynamically in order to generate less communication among the processors, provided that the system runs for enough execution time in order to amortize the migration overhead.In this work, a combination of allocation heuristics from the domain of Distributed Computing Systems is applied, for instance bin-packing and linear clustering algorithms. Results shows that applying task reallocation using the Worst-Fit and Linear Clustering combination reduces the energy consumption and deadline miss ratio by 17% and 37%, respectively, using the copy task migration model.

O software vem se tornando cada vez mais o principal fator de custo no desenvolvimento de dispositivos embarcados. Atualmente, com o aumento aumentando da complexidade dos sistemas embarcados, se faz necessário o uso de técnicas e metodologias que, ao mesmo tempo, permitam o aumento da produtividade do desenvolvimento de software e permitam manipular as restrições dos sistemas embarcados como tamanho de memória, comportamento de tempo real, desempenho e energia. A análise e projeto orientado a objetos são altamente conhecidos e utilizados na comunidade de engenharia de software. Este paradigma auxilia no desenvolvimento e manutenção do software, porém apresenta uma signi cativa sobrecarga em termos de memória, desempenho e tamanho do código. Esta tese introduz uma metodologia e um conjunto de ferramentas que permitem o uso concomitante de orientação a objetos e os diferentes requisitos dos sistemas embarcados. Para atingir este objetivo, esta tese apresenta uma metodologia para exploração de software embarcado orientado a objetos que permite melhoria em diferentes níveis do processo de desenvolvimento do software baseado em diferentes implementações do mesmo processador. Os resultados da metodologia são apresentados baseados na aplicação de um tocador de MP3. / Software is increasingly becoming the major cost factor for embedded devices. Nowadays, with the growing complexity of embedded systems, it is necessary to use techniques and methodologies that can, at the same time, increase software productivity and manipulate embedded systems constraints - like memory footprint, real-time behavior, performance and energy. Object-oriented modeling and design is a widely known methodology in software engineering. This paradigm may satisfy software portability and maintainability requirements, but it presents overhead in terms of memory, performance and code size. This thesis introduces a methodology and a set of tools that can deal, at the same time, with object orientation and di erent embedded systems requirements. To achieve this goal, the thesis presents a methodology to explore object-oriented embedded software improving di erent levels in the software design based on di erent implementations with the same processor. The results of the methodology are presented based on an MP3 player application.

Les progrès dans la fabrication des systèmes de calcul reconfigurables de type « Field Programmable Gate Arrays » (FPGA) s’appuient sur la technologie CMOS, ce qui engendre une consommation des puces élevée. Des nouveaux paradigmes de calcul sont désormais nécessaires pour remplacer les architectures de calcul traditionnel ayant une faible performance et une haute consommation énergétique. En particulier, optique intégré pourrait offrir des solutions intéressantes. Beaucoup de travail sont déjà adressées à l’utilisation d’interconnexion optique pour relaxer les contraintes intrinsèques d’interconnexion électronique. Dans ce contexte, nous proposons une nouvelle architecture de calcul reconfigurable optique, la « optical lookup table » (OLUT), qui est une implémentation optique de la lookup table (LUT). Elle améliore significativement la latence et la consommation énergétique par rapport aux architectures de calcul d’optique actuelles tel que RDL (« reconfigurable directed logic »), en utilisant le spectre de la lumière au travers de la technologie WDM. Nous proposons une méthodologie de conception multi-niveaux permettant l'explorer l’espace de conception et ainsi de réduire la consommation énergétique tout en garantissant une fiabilité élevée des calculs (BER~10-18). Les résultats indiquent que l’OLUT permet une consommation inférieure à 100fJ/opération logique, ce qui répondait en partie aux besoins d’un FPGA tout-optique à l’avenir. / Advances in the design of high performance silicon chips for reconfigurable computing, i.e. Field Programmable Gate Arrays (FPGAs), rely on CMOS technology and are essentially limited by energy dissipation. New design paradigms are mandatory to replace traditional, slow and power consuming, electronic computing architectures. Integrated optics, in particular, could offer attractive solutions. Many related works already addressed the use of optical on-chip interconnects to help overcome the technology limitations of electrical interconnects. Integrated silicon photonics also has the potential for realizing high performance computing architectures. In this context, we present an energy-efficient on-chip reconfigurable photonic logic architecture, the so-called OLUT, which is an optical core implementation of a lookup table. It offers significant improvement in latency and power consumption with respect to optical directed logic architectures, through allowing the use of wavelength division multiplexing (WDM) for computation parallelism. We proposed a multi-level modeling approach based on the design space exploration that elucidates the optical device characteristics needed to produce a computing architecture with high computation reliability (BER~10-18) and low energy dissipation. Analytical results demonstrate the potential of the resulting OLUT implementation to reach <100 fJ/bit per logic operation, which may meet future demands for on-chip optical FPGAs.

This project aims to explore what the brand Land Rover could stand for in the future. The brands rich history of exploring unconquered terrain earned it admiration and desirability all around the world. Further extending it's reach onto new worlds is within reach. In the 2030s the first manned missions to Mars are planned. The first arrivers will have exploration vehicles, that are limited in range and capability. To really explore the planet, vehicles with greater off-road capability and range will be needed. The vehicles also need to allow the expedition crews to stay in the vehicle for longer periods comfortably and also offer extended life support on multi-week long journeys.With this project I am exploring possible answers to face the harsh conditions on Mars. Furthermore, the vehicle and it's features project a vision of what a future off-road driving experience could be.

Los diseños multi-núcleo se están convirtiendo en la solución más popular a la mayoría de las limitaciones de los diseños mono-núcleo. Un diseño multi-núcleo sigue el paradigma de diseño conocido como Sistema dentro del Chip (o SoC , del inglés System on-Chip), en el cuál varios núcleos se integran en un mismo chip. Las prestaciones de un diseño SoC dependen en gran medida de la infraestructura de interconexión que implemente. En este contexto, el paradigma de diseño conocido como red dentro del chip (o NoC, del inglés Network on-Chip) surge como una solución a los desafíos de interconexión presentes en los nuevos diseños de tipo SoC. Para un diseño concreto, el alto número de posibles soluciones basadas en NoCs incrementa la complejidad de analizar el espacio de diseño y de elegir la NoC óptima. La solución más común a este problema pasa por la utilización de herramientas de alto nivel para la obtención de estimaciones sobre las prestaciones de cada posible solución, que posteriormente serán utilizadas por el diseñador para cribar el espacio de diseño en las primeras etapas del proceso de diseño. Pero hay una gran diferencia entre las prestaciones estimadas por herramientas de alto nivel y las prestaciones reales obtenidas una vez el sistema se implementa. Este trabajo se centra en el desarrollo de nuevas herramientas de alto nivel de diseño, modelado y simulación de NoCs, con el fin de cribar el espacio de diseño de los candidatos menos atractivos. En un primer paso, nos centraremos en el diseño y desarrollo de una plataforma experimental para analizar arquitecturas alternativas para el diseño de NoCs de forma que permitan evaluar cualquier punto del espacio de diseño de forma rápida y precisa, mediante la anotación de algunos parámetros claves del proceso de síntesis física. En el segundo paso, se revisaron arquitecturas y técnicas de diseño adoptadas del dominio de las redes de interconexión fuera del chip, seleccionando las más prometedoras y, en algunos casos, explotando las características propias de las redes dentro de chip para obtener nuevas soluciones. Este paso, preliminar al desarrollo de la herramienta para la realización de exploraciones del espacio de diseño (o herramientas DSE, del inglés Design Space Exploration), tiene como objetivo depurar las técnicas para la abstracción de los efectos de la implementación física de las NoCs sobre sus prestaciones. / Gilabert Villamón, F. (2011). Design Space Exploration for Networks On-chip [Tesis doctoral no publicada]. Universitat Politècnica de València. https://doi.org/10.4995/Thesis/10251/11521 / Palancia

The initial phases of the design process -- including interactions with stakeholders, ideation of concept candidates, and the selection of the best candidates --- have a large impact on the success of a project as a whole. Much of the value generated during these phases comes from the designers' exploration of the design space as they create concepts for the final solution. Unfortunately, an entire dimension of the design space is often ignored during the initial phases of the design process -- the tactics dimension. Engineers tend to emphasize the design of technology in their work, while paying less attention to how that technology is used. By adding tactics to technology as two dimensions of the design space and creating the Tech/Tac plot as a means for visualizing those dimensions, the designer's ability to visualize, understand, and explore an expanded design space is improved. In this paper, we introduce a deliberate design-space structure that can help teams generate and evaluate integrated Tech/Tac concepts. The structure improves concept exploration during the early phases of the design process by harnessing the information provided by a two-dimensional, structured design space. This design space is represented here as a vector space with a basis of technology and tactics. Also presented are definitions and principles that facilitate the use of the technology-tactics framework to represent the design space in various useful ways. Six tests were carried out during this research to develop and evaluate the structure. The final instantiation of the concepts presented in this paper has been shown to be meaningful to design teams during ideation.

<p>Computer Vision is a mathematical tool formulated to extend human vision to machines. This tool can perform various tasks such as object classification, object tracking, motion estimation, and image segmentation. These tasks find their use in many applications, namely robotics, self-driving cars, augmented reality, and mobile applications. However, opposed to the traditional technique of incorporating handcrafted features to understand images, convolution neural networks are being used to perform the same function. Computer vision applications widely use CNNs due to their stellar performance in interpreting images. Over the years, there have been numerous advancements in machine learning, particularly to CNNs. However, the need to improve their accuracy, model size and complexity increased, making their deployment in restricted environments a challenge. Many researchers proposed techniques to reduce the size of CNN while still retaining its accuracy. Few of these include network quantization, pruning, low rank, and sparse decomposition and knowledge distillation. Some methods developed efficient models from scratch. This thesis achieves a similar goal using design space exploration techniques on the latest variant of MobileNets, MobileNet V3. Using Depthwise Pointwise Depthwise (DPD) blocks, escalation in the number of expansion filters in some layers and mish activation function MobileNet V3 is reduced to 84.96% in size and made 0.2% more accurate. Furthermore, it is deployed in NXP i.MX RT1060 for image classification on CIFAR-10 dataset.</p>

Indiana University-Purdue University Indianapolis (IUPUI) / Computer Vision is a mathematical tool formulated to extend human vision to machines. This tool can perform various tasks such as object classification, object tracking, motion estimation, and image segmentation. These tasks find their use in many applications, namely robotics, self-driving cars, augmented reality, and mobile applications. However, opposed to the traditional technique of incorporating handcrafted features to understand images, convolution neural networks are being used to perform the same function. Computer vision applications widely use CNNs due to their stellar performance in interpreting images. Over the years, there have been numerous advancements in machine learning, particularly to CNNs.However, the need to improve their accuracy, model size and complexity increased, making their deployment in restricted environments a challenge. Many researchers proposed techniques to reduce the size of CNN while still retaining its accuracy. Few of these include network quantization, pruning, low rank, and sparse decomposition and knowledge distillation. Some methods developed efficient models from scratch. This thesis achieves a similar goal using design space exploration techniques on the latest variant of MobileNets, MobileNet V3. Using DPD blocks, escalation in the number of expansion filters in some layers and mish activation function MobileNet V3 is reduced to 84.96% in size and made 0.2% more accurate. Furthermore, it is deployed in NXP i.MX RT1060 for image classification on CIFAR-10 dataset.

CPU cache hierarchies are the central solution in bridging the memory wall. A proper understanding of how to trade-off their high cost against performance can lead to cost-savings without sacrificing performance.Due to the combinatorial nature of the problem, there exist a large number of configurations to investigate, making design space exploration slow and cumbersome. To improve this process, this Thesis develops and evaluates a model for optimally trading-off cost and performance of CPU cache hierarchies, named the Optimal Cache Problem (OCP), in the form of a Non-linear Integer Problem. A second goal of this work is the development of an efficient solver for the OCP, which was found to be a branch &amp; bound algorithm and proven to function correctly. Experiments were conducted to empirically analyse and validate the model and to showcase possible use-cases. There, it was possible to ascribe the model outputs on measurable performance metrics. The model succeeded in formalising the inherent trade-off between cost and performance in a way that allows for an efficient and complete search of the configuration space of possible cache hierarchies. In future work, the model needs to be refined and extended to allow for the simultaneous analysis of multiple programs.

When designing an engineering part, better decisions are made by exploring the entire space of design variations. This design space exploration (DSE) may be accomplished manually or via optimization. In engineering, evaluating a design during DSE often consists of running expensive simulations, such as finite element analysis (FEA) in order to understand the structural response to design changes. The computational cost of these simulations can make thorough DSE infeasible, and only a relatively small subset of the designs are explored. Surrogate models have been used to make cheap predictions of certain simulation results. Commonly, these models only predict single values (SV) that are meant to represent an entire part's response, such as a maximum stress or average displacement. However, these single values cannot return a complete prediction of the detailed nodal results of these simulations. Recently, surrogate models have been developed that can predict the full field (FF) of nodal responses. These FF surrogate models have the potential to make thorough and detailed DSE much more feasible and introduce further design benefits. However, these FF surrogate models have not yet been applied to real engineering activities or been demonstrated in DSE contexts, nor have they been directly compared with SV surrogate models in terms of accuracy and benefits.This thesis seeks to build confidence in FF surrogate models for engineering work by applying FF surrogate models to real DSE and engineering activities and exploring their comparative benefits with SV surrogate models. A user experiment which explores the effects of FF surrogate models in simple DSE activities helps to validate previous claims that FF surrogate models can enable interactive DSE. FF surrogate models are used to create Goodman diagrams for fatigue analysis, and found to be more accurate than SV surrogate models in predicting fatigue risk. Mode shapes are predicted and the accuracy of mode comparison predictions are found to require a larger amount of training samples when the data is highly nonlinear than do SV surrogate models. Finally, FF surrogate models enable spatially-defined objectives and constraints in optimization routines that efficiently search a design space and improve designs.The studies in this work present many unique FF-enabled design benefits for real engineering work. These include predicting a complete (rather than a summary) response, enabling interactive DSE of complex simulations, new three-dimensional visualizations of analysis results, and increased accuracy.