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Many hydrocarbon detection techniques have been developed for decades and one of the most efficient techniques for hydrocarbon exploration in recent years is well known as amplitude versus offset analysis (AVO). However, AVO analysis does not always result in successful hydrocarbon finds because abnormal seismic amplitude variations can sometimes be caused by other factors, such as alternative lithology and residual hydrocarbons in certain depositional environments. Furthermore, not all gas fields are associated with obvious AVO anomalies. Therefore, new techniques should be applied to combine with AVO for hydrocarbon detection. In my thesis, I, through case studies, intend to investigate and validate the wave decomposition technique as a new tool for hydrocarbon detection which decomposes seismic wave into different frequency contents and may help identify better the amplitude anomalies associated with hydrocarbon occurrence for each frequency due to seismic attenuation. The wavelet decomposition analysis technique has been applied in two geological settings in my study: clastic reservoir and carbonate reservoir. Results from both cases indicate that the wavelet decomposition analysis technique can be used for hydrocarbon detection effectively if the seismic data quality is good. This technique can be directly applied to the processed 2D and 3D pre-stack/post-stack data sets (1) to detect hydrocarbon zones in both clastic and carbonate reservoirs by analyzing the low frequency signals in the decomposed domain and (2) to identify thin beds by analyzing the high frequency signals in the decomposed domain. In favorable cases, the method may possibly help separate oil from water in high-porosity and high-permeability carbonate reservoirs deeply buried underground. Therefore, the wavelet analysis would be a powerful tool to assist geological interpretation and to reduce risk for hydrocarbon exploration.

The technology for driver safety has been developed in many fields such as airbag system, Anti-lock Braking System or ABS, ultrasonic warning system, and others. Recently, some of the automobile companies have introduced a new feature of driver safety systems. This new system is to make the car slower if it finds a driver’s drowsy eyes. For instance, Toyota Motor Corporation announced that it has given its pre-crash safety system the ability to determine whether a driver’s eyes are properly open with an eye monitor. This paper is focusing on finding a driver’s drowsy eyes by using face detection technology. The human face is a dynamic object and has a high degree of variability; that is why face detection is considered a difficult problem in computer vision. Even with the difficulty of this problem, scientists and computer programmers have developed and improved the face detection technologies. This paper also introduces some algorithms to find faces or eyes and compares algorithm’s characteristics. Once we find a face in a sequence of images, the matter is to find drowsy eyes in the driver safety system. This system can slow a car or alert the user not to sleep; that is the purpose of the pre-crash safety system. This paper introduces the VeriLook SDK, which is used for finding a driver’s face in the real time driver safety system. With several experiments, this paper also introduces a new way to find drowsy eyes by AOI,Area of Interest. This algorithm improves the speed of finding drowsy eyes and the consumption of memory use without using any object classification methods or matching eye templates. Moreover, this system has a higher accuracy of classification than others.

Este trabalho apresenta uma ferramenta configurável, denominada de CFT-tool, capaz de aplicar automaticamente técnicas de detecção de erros em software com o objetivo de proteger processadores com diferentes arquiteturas e organizações contra falhas transientes no hardware. As técnicas baseadas em redundância e comparação são aplicadas pela CFT-tool no código assembly de um programa desprotegido, compilado para a arquitetura alvo. A ferramenta desenvolvida foi validada utilizando dois processadores distintos: miniMIPS e LEON3. O processador miniMIPS foi utilizado para verificar a eficiência, em termos de taxa de detecção de erros, tempo de execução e ocupação de memória, das técnicas de detecção em software aplicadas pela CFT-tool, comparando os resultados obtidos com os presentes na literatura. O processador LEON3 foi selecionado por ser amplamente utilizado em aplicações espaciais e por ser baseado em uma arquitetura diferente da arquitetura do processador miniMIPS. Com o processador LEON3 é verificada a configurabilidade da CFT-tool, isto é, a capacidade dela de aplicar técnicas de detecção em software em um código compilado para um diferente processador, o mantendo funcional e sendo capaz de detectar erros. A CFT-tool pode ser utilizada para proteger programas para outras arquiteturas e organizações através da modificação dos arquivos de configuração da ferramenta. A configuração das técnicas é definida segundo as especificações da aplicação, recursos do processador e seleções do usuário. Programas foram protegidos e falhas foram injetadas em nível lógico em ambos os processadores. Para o processador miniMIPS, as taxas de detecção de erros, os tempos de execução e as ocupações de memórias dos programas protegidos se mostraram compatíveis com os resultados presentes na literatura. Resultados semelhantes foram encontrados para o processador LEON3. Diferenças entre os resultados ocorrem devido às características da arquitetura. A ferramenta CFT-tool por ser configurável pode proteger o código na integralidade ou selecionar partes do código e registradores que serão redundantes e protegidos. A vantagem de proteger parte do código é reduzir o custo final em termos de tempo de processamento e ocupação de memória. Uma análise do impacto da seleção seletiva de registradores na taxa de detecção de erros é apresentada. E diretivas de alcançar um comprometimento ótimo entre quantidade de registradores protegidos, taxa de detecção de erros e custo são discutidas. / This work presents a configurable tool, called CFT-tool, capable of automatically applying software-based error detection techniques aiming to protect processors with different architectures and organizations against transient faults in the hardware. The techniques are based on redundancy and comparison. They are applied by CFT-tool in the assembly code of an unprotected program, compiled to the target architecture. The developed tool was validated using two distinct processors: miniMIPS and LEON3. The miniMIPS processor has been utilized to verify the efficiency of the software-based techniques applied by CFT-tool in the assembly code of unprotected programs in terms of error detection rate, runtime and memory occupation, comparing the obtained results with those presented in the literature. The LEON3 processor was selected because it is largely adopted in space applications and because it is based on a different architecture that miniMIPS processor. The configurability of the CFT-tool is verified with the LEON3 processor, that is, the capability of the tool at applying software-based detection techniques in a code compiled to a different processor, maintaining it functional and capable of detecting errors. The CFT-tool can be utilized to protect programs compiled to other architectures and organizations by modifying the configuration files of the tool. The configuration of the techniques is defined by the specifications of the application, processor resources and selections of the user. Programs were protected and faults were injected in logical level in both processors. When using the miniMIPS processor, the error detection rates, runtimes and memory occupations of the protected programs are comparable to the results presents in the literature. Similar results are reached with the LEON3 processor. Differences between the results are due to architecture features. The CFT-tool can be configurable to protect the entire code or to select portions of the code or registers that will be redundant and protected. The advantage of protecting portions of the code is to reduce the final cost in terms of runtime and memory occupation. An analysis of the impact of selective selection of registers in the error detection rate is also presented. And policies to reach an optimum committal between amount of protected registers, error detection rate and cost are discussed.

Este trabalho apresenta uma ferramenta configurável, denominada de CFT-tool, capaz de aplicar automaticamente técnicas de detecção de erros em software com o objetivo de proteger processadores com diferentes arquiteturas e organizações contra falhas transientes no hardware. As técnicas baseadas em redundância e comparação são aplicadas pela CFT-tool no código assembly de um programa desprotegido, compilado para a arquitetura alvo. A ferramenta desenvolvida foi validada utilizando dois processadores distintos: miniMIPS e LEON3. O processador miniMIPS foi utilizado para verificar a eficiência, em termos de taxa de detecção de erros, tempo de execução e ocupação de memória, das técnicas de detecção em software aplicadas pela CFT-tool, comparando os resultados obtidos com os presentes na literatura. O processador LEON3 foi selecionado por ser amplamente utilizado em aplicações espaciais e por ser baseado em uma arquitetura diferente da arquitetura do processador miniMIPS. Com o processador LEON3 é verificada a configurabilidade da CFT-tool, isto é, a capacidade dela de aplicar técnicas de detecção em software em um código compilado para um diferente processador, o mantendo funcional e sendo capaz de detectar erros. A CFT-tool pode ser utilizada para proteger programas para outras arquiteturas e organizações através da modificação dos arquivos de configuração da ferramenta. A configuração das técnicas é definida segundo as especificações da aplicação, recursos do processador e seleções do usuário. Programas foram protegidos e falhas foram injetadas em nível lógico em ambos os processadores. Para o processador miniMIPS, as taxas de detecção de erros, os tempos de execução e as ocupações de memórias dos programas protegidos se mostraram compatíveis com os resultados presentes na literatura. Resultados semelhantes foram encontrados para o processador LEON3. Diferenças entre os resultados ocorrem devido às características da arquitetura. A ferramenta CFT-tool por ser configurável pode proteger o código na integralidade ou selecionar partes do código e registradores que serão redundantes e protegidos. A vantagem de proteger parte do código é reduzir o custo final em termos de tempo de processamento e ocupação de memória. Uma análise do impacto da seleção seletiva de registradores na taxa de detecção de erros é apresentada. E diretivas de alcançar um comprometimento ótimo entre quantidade de registradores protegidos, taxa de detecção de erros e custo são discutidas. / This work presents a configurable tool, called CFT-tool, capable of automatically applying software-based error detection techniques aiming to protect processors with different architectures and organizations against transient faults in the hardware. The techniques are based on redundancy and comparison. They are applied by CFT-tool in the assembly code of an unprotected program, compiled to the target architecture. The developed tool was validated using two distinct processors: miniMIPS and LEON3. The miniMIPS processor has been utilized to verify the efficiency of the software-based techniques applied by CFT-tool in the assembly code of unprotected programs in terms of error detection rate, runtime and memory occupation, comparing the obtained results with those presented in the literature. The LEON3 processor was selected because it is largely adopted in space applications and because it is based on a different architecture that miniMIPS processor. The configurability of the CFT-tool is verified with the LEON3 processor, that is, the capability of the tool at applying software-based detection techniques in a code compiled to a different processor, maintaining it functional and capable of detecting errors. The CFT-tool can be utilized to protect programs compiled to other architectures and organizations by modifying the configuration files of the tool. The configuration of the techniques is defined by the specifications of the application, processor resources and selections of the user. Programs were protected and faults were injected in logical level in both processors. When using the miniMIPS processor, the error detection rates, runtimes and memory occupations of the protected programs are comparable to the results presents in the literature. Similar results are reached with the LEON3 processor. Differences between the results are due to architecture features. The CFT-tool can be configurable to protect the entire code or to select portions of the code or registers that will be redundant and protected. The advantage of protecting portions of the code is to reduce the final cost in terms of runtime and memory occupation. An analysis of the impact of selective selection of registers in the error detection rate is also presented. And policies to reach an optimum committal between amount of protected registers, error detection rate and cost are discussed.

Este trabalho apresenta uma ferramenta configurável, denominada de CFT-tool, capaz de aplicar automaticamente técnicas de detecção de erros em software com o objetivo de proteger processadores com diferentes arquiteturas e organizações contra falhas transientes no hardware. As técnicas baseadas em redundância e comparação são aplicadas pela CFT-tool no código assembly de um programa desprotegido, compilado para a arquitetura alvo. A ferramenta desenvolvida foi validada utilizando dois processadores distintos: miniMIPS e LEON3. O processador miniMIPS foi utilizado para verificar a eficiência, em termos de taxa de detecção de erros, tempo de execução e ocupação de memória, das técnicas de detecção em software aplicadas pela CFT-tool, comparando os resultados obtidos com os presentes na literatura. O processador LEON3 foi selecionado por ser amplamente utilizado em aplicações espaciais e por ser baseado em uma arquitetura diferente da arquitetura do processador miniMIPS. Com o processador LEON3 é verificada a configurabilidade da CFT-tool, isto é, a capacidade dela de aplicar técnicas de detecção em software em um código compilado para um diferente processador, o mantendo funcional e sendo capaz de detectar erros. A CFT-tool pode ser utilizada para proteger programas para outras arquiteturas e organizações através da modificação dos arquivos de configuração da ferramenta. A configuração das técnicas é definida segundo as especificações da aplicação, recursos do processador e seleções do usuário. Programas foram protegidos e falhas foram injetadas em nível lógico em ambos os processadores. Para o processador miniMIPS, as taxas de detecção de erros, os tempos de execução e as ocupações de memórias dos programas protegidos se mostraram compatíveis com os resultados presentes na literatura. Resultados semelhantes foram encontrados para o processador LEON3. Diferenças entre os resultados ocorrem devido às características da arquitetura. A ferramenta CFT-tool por ser configurável pode proteger o código na integralidade ou selecionar partes do código e registradores que serão redundantes e protegidos. A vantagem de proteger parte do código é reduzir o custo final em termos de tempo de processamento e ocupação de memória. Uma análise do impacto da seleção seletiva de registradores na taxa de detecção de erros é apresentada. E diretivas de alcançar um comprometimento ótimo entre quantidade de registradores protegidos, taxa de detecção de erros e custo são discutidas. / This work presents a configurable tool, called CFT-tool, capable of automatically applying software-based error detection techniques aiming to protect processors with different architectures and organizations against transient faults in the hardware. The techniques are based on redundancy and comparison. They are applied by CFT-tool in the assembly code of an unprotected program, compiled to the target architecture. The developed tool was validated using two distinct processors: miniMIPS and LEON3. The miniMIPS processor has been utilized to verify the efficiency of the software-based techniques applied by CFT-tool in the assembly code of unprotected programs in terms of error detection rate, runtime and memory occupation, comparing the obtained results with those presented in the literature. The LEON3 processor was selected because it is largely adopted in space applications and because it is based on a different architecture that miniMIPS processor. The configurability of the CFT-tool is verified with the LEON3 processor, that is, the capability of the tool at applying software-based detection techniques in a code compiled to a different processor, maintaining it functional and capable of detecting errors. The CFT-tool can be utilized to protect programs compiled to other architectures and organizations by modifying the configuration files of the tool. The configuration of the techniques is defined by the specifications of the application, processor resources and selections of the user. Programs were protected and faults were injected in logical level in both processors. When using the miniMIPS processor, the error detection rates, runtimes and memory occupations of the protected programs are comparable to the results presents in the literature. Similar results are reached with the LEON3 processor. Differences between the results are due to architecture features. The CFT-tool can be configurable to protect the entire code or to select portions of the code or registers that will be redundant and protected. The advantage of protecting portions of the code is to reduce the final cost in terms of runtime and memory occupation. An analysis of the impact of selective selection of registers in the error detection rate is also presented. And policies to reach an optimum committal between amount of protected registers, error detection rate and cost are discussed.

Hepatitis A virus (HAV) is a non-enveloped, positively charged single stranded RNA hepatotropic agent from the family Picornaviridae, and the sole member of the genus Hepatovirus. There is only one HAV serotype but there are seven genotypes. Hepatitis A (HA) infection is usually self-limiting and the severity of the illness is age dependant. In children, infection with HAV is usually asymptomatic, while most adults and immunocompromised patients develop moderate to severe clinical disease. HA is endemic in South Africa (SA) with 100% of children from the lower socio-economic population acquiring immunity before the age of 10. With the current trends in urbanisation, a change in the epidemic vulnerability of the SA population can be expected. HAV is predominantly transmitted by the faecal-oral route and contaminated food and water are important sources of infection. However, the contribution of waterborne HAV to the burden of HA disease in SA is unknown. The aims of this investigation were to assess techniques for the recovery, isolation and detection of HAV from water sources. Thereafter these techniques were applied to estimate the potential risk of infection posed to communities using the water sources for recreational and domestic purposes. This would elucidate whether or not water plays a role in the spread of HAV infection in SA. An effective and sensitive concentration method is fundamental to the successful detection of HAV in water sources. Three primary recovery and two secondary concentration techniques were investigated in this study. An in-house modified glass wool technique, using 15g of glass wool and with the addition of three metal gauze grids at 5g intervals, proved to be the most sufficient and cost effective technique for the primary recovery of HAV from water sources. The packing density of the glass wool and positioning of the grids proved to be essential for efficient HAV recovery. A polyethylene glycol/sodium chloride secondary concentration technique proved to be more cost effective than commercial centrifugal devices. Combinations of cell cultures, propagation conditions, RNA extraction protocols and detection techniques were assessed for the isolation and detection of HAV. A combination of FRhK-4R cell culture propagation and reverse transcription-polymerase chain reaction-oligonucleotide probe assay was demonstrated to be the simple, most efficient technique for the detection of HAV. The nucleotide sequences of HAV strains from water sources and clinical specimens were compared to ascertain whether the strains from water were a potential source of infection. Although the majority of clinical strains clustered seperately from the water strains, one strain from an asymptomatic patient was identical to a number of strains from water. This suggests that HAV in the environment is a potential source of infection in SA. To assess the potential risk of infection constituted by HAV to persons using surface dam and river water for domestic and recreational purposes, a deterministic exponential risk assessment model which works with mean values and conservative assumptions was applied. Results indicated a minimal risk of infection to the higher socio-economic, non-immune population using the water for recreational purposes, if 100 ml of water was ingested per day. No risk was identified for the lower socio-economic, predominantly immune, population who uses the same water sources for domestic and drinking purposes. This study represents the first comprehensive data on risk of infection constituted by waterborne HAV in SA. / Dissertation (MSc)--University of Pretoria, 2008. / Medical Virology / unrestricted

Society is going through a change to be more sustainable, and one big step in that process is to convert the power grid from convectional power generation to increased part of renewable energy sources. Renewable energy sources often require power electronics such as converters to connect to the power grid, and power electronics can cause interference in the grid. This development in Sweden and rest of the Nordic countries is driven by the large increase of load based on power electronics. To maintain a stable power grid, it is essential to detect disturbances through measurement techniques adapted to the challenges that may arise.   The measurement techniques in the Swedish power grid have historically been based on power quality meters and RMS-based measurements, and this thesis focuses on the disturbances that RMS-based measurements may fail to detect. The objective is to compare the RMS-based measurements techniques available in the power grid with waveform measurement techniques developed to see how they could detect disturbances in the power grid. The first research question pertains to the characteristic frequency bandwidths within which a power system typically operates, and what frequency bandwidths a system could have with a significant amount of power electronics installed. The second research question concerns the measurement techniques.   This work consists of four main parts: bandwidth analysis of control systems for voltage source converter, RMS vs waveform detection techniques, interaction between converter and voltage perturbation, and realistic phenomena studies. The bandwidth analysis aims to determine the frequency range expected in future power systems, which in turn informs the minimum detection capabilities required for measurement techniques. This was achieved through calculations involving the control loops of converters, including the inner current control loop, outer control loop, and phase locked loop. Bode diagrams were generated for each control loop, with variables manipulated, and the short circuit ratio adjusted to determine the bandwidth of the control loop.   The RMS vs waveform detection techniques  phase was central to the study, involving simulations imitating various phenomena that could occur in the power grid. This was accomplished using two ideal sources and examining their interactions. The simulations included frequency perturbations, amplitude perturbations, and added oscillations apparent at sub-synchronous, super-synchronous, and high super-synchronous frequencies. Simulation results were presented for both RMS and waveform based defection techniques, simulating different reporting rates to mimic real measurement tools.   The third and fourth parts involved validating the RMS vs waveform detection techniques  results using real-case simulations. An HVDC model was employed to simulate the effects of voltage perturbation and observe the coupling over frequency mechanism. The same HVDC model was also used to simulate phenomena occurring in weak grids. Additionally, a wind park model was utilized to simulate the induction generator effect phenomena.   The findings reveal that the bandwidth of a power system undergoes significant expansion as the proportion of power electronics increases in the grid. Specifically, analysis of converter indicates a shift from under 50 Hz to several kHz in systems dominated by synchronous generators versus those dominated by power electronics. To effectively detect higher frequency oscillations within the grid, waveform measurement tools become essential, as classical RMS measurement tools are inadequate for capturing oscillations originating from power electronics. As power systems evolve towards dominance by power electronics, it becomes imperative to develop measurement systems capable of accurately detecting high frequency oscillations.   The recommendation of this thesis is to invest in waveform measurement tools alongside the already existing RMS-based ones to enhance the detection of disturbances, particularly those with super synchronous frequencies, addressing future power grid challenges.

A diminuição no tamanho dos transistores vem aumentando cada vez mais o número de funções que os dispositivos eletrônicos podem realizar. Apesar da diminuição do tamanho mínimo dos transistores, a velocidade máxima dos circuitos não consegue seguir a mesma taxa de aumento. Um dos grandes culpados apontados pelos pesquisadores são as interconexões entre os transistores e também entre os componentes. O aumento no número de interconexões dos circuitos traz consigo um significativo aumento do cosumo de energia, aumento do atraso de propagação dos sinais, além de um aumento da complexidade e custo do projeto dos circuitos integrados. Como uma possível solução a este problema é proposta a utilização de lógica multivalorada, mais especificamente, a lógica quaternária. Os dispositivos FPGAs são caracterizados principalmente pela grande flexibilidade que oferecem aos projetistas de sistemas digitais. Entretanto, com o avanço nas tecnologias de fabricação de circuitos integrados e diminuição das dimensões de fabricação, os problemas relacionados ao grande número de interconexões são uma preocupação para as próximas tecnologias de FPGAs. As tecnologias menores que 90nm possuem um grande aumento na taxa de erros dos circuitos, na lógica combinacional e sequencial. Apesar de algumas potenciais soluções começara a ser investigadas pela comunidade, a busca por circuitos tolerantes a erros induzidos por radiação, sem penalidades no desempenho, área ou potência, ainda é um assunto de pesquisa em aberto. Este trabalho propõe o uso de circuitos quaternários com modificações para tolerar falhas provenientes de eventos transientes. Como principal contribuição deste trabalho destaca-se o desenvolvimento de uma CLB (do inglês Configurable Logic Block) quaternária capaz de suportar eventos transientes e, na possibilidade de um erro, evitá-lo ou corrigi-lo. / The decrease in transistor size is increasing the number of functions that can be performed by the electronic devices. Despite this reduction in the transistors minimum size, the circuit’s speed does not follow the same rate. One of the major reasons pointed out by researchers are the interconnections between the transistors and between the components. The increase in the number of circuit interconnections brings a significant increase in energy consumption, propagation delay of signals, and an increase in the complexity and cost of new technologies IC designs. As a possible solution to this problem the use of multivalued logic is being proposed, more specifically, the quaternary logic. FPGA devices are characterized mainly by offering greater flexibility to designers of digital systems. However, with the advance in IC manufacturing technologies and the reduced size of the minimum fabricated dimensions, the problems related to the large number of interconnections are a concern for future technologies of FPGAs. The sub 90nm technologies have a large increase in the error rate of its functions for the combinational and sequential logic. Although potential solutions are being investigated by the community, the search for circuits tolerant to radiation induced errors, without performance, area, or power penalties, is still an open research issue. This work proposes the use of quaternary circuits with modifications to tolerate faults from transient events. The main contribution of this work is the development of a quaternary CLB (Configurable Logic Block) able to withstand transient events and the occurrence of soft errors.