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L'évolution des technologies microélectroniques voire déca-nanoélectroniques conduit simultanément à des tensions d'alimentation toujours plus faibles et à des quantités de transistors toujours plus grandes. De ce fait, les courants d'alimentation augmentent sous une tension d'alimentation qui diminue, situation qui exacerbe la sensibilité des circuits intégrés au bruit d'alimentation. Un bruit d'alimentation excessif se traduit par une augmentation du retard des portes logiques pouvant finalement produire des fautes de retard. Un bruit d'alimentation provoqué par des courants circulant dans les résistances parasites du Réseau de Distribution d'Alimentation est communément référencé sous la dénomination d'IR-Drop.Cette thèse s'intéresse à la modélisation et à la simulation de circuits logiques avec prise en compte du phénomène d'IR-Drop. Un algorithme original est tout d'abord proposé en vue d'une simulation de type ‘event-driven' du block logique sous test, en tenant compte de l'impact de l'ensemble du circuit intégré sur l'IR-Drop du block considéré. Dans ce contexte, des modèles précis et efficaces sont développés pour les courants générés par les portes en commutation, pour la propagation de ces courants au travers du réseau de distribution et pour les retards des portes logiques. D'abord, une procédure de pré-caractérisation des courants dynamiques, statiques et des retards est décrite. Ensuite, une seconde procédure est proposée pour caractériser la propagation des courants au travers du réseau de distribution. Nos modèles ont été implantés dans une première version du simulateur développé par nos collègues de Passau dans le cadre d'une collaboration. Enfin, l'impact des éléments capacitifs parasites du réseau de distribution est analysé et une procédure pour caractériser la propagation des courants est envisagée. / Scaling technology in deep-submicron has reduced the voltage supply level and increased the number of transistors in the chip, increasing the power supply noise sensitivity of the ICs. Excessive power supply noise affects the timing performance increasing the gate delay and may cause timing faults. Specifically, power supply noise induced by the currents that flow through the resistive parasitic elements of the Power Distribution Network (PDN) is called IR-Drop. This thesis deals with the modelling and simulation of logic circuits in the context of IR-drop. An original algorithm is proposed allowing to perform an event-driven delay simulation of the logic Block Under Test (BUT) while taking into account the whole chip IR-drop impact on the simulated block. To do so, we develop accurate and efficient electrical models for the currents generated by the switching gates, the propagation of the current draw through the PDN and the gate delays. First, the pre-characterization process for the dynamic currents, static currents and gate delays is described to generate a gate library. Then, another pre-characterization procedure is suggested to estimate the current distribution through the resistive PDN model. Our models are implemented in a first version of the simulator by the University of Passau in the context of a project collaboration. In addition, the impact of the parasitic capacitive elements of the PDN is analyzed and a procedure to derive the current distribution in a resistive-capacitive PDN model is proposed.

Scaling technology in deep-submicron has reduced the voltage supply level and increased the number of transistors in the chip, increasing the power supply noise sensitivity of the ICs. Excessive power supply noise affects the timing performance increasing the gate delay and may cause timing faults. Specifically, power supply noise induced by the currents that flow through the resistive parasitic elements of the Power Distribution Network (PDN) is called IR-Drop. This thesis deals with the modelling and simulation of logic circuits in the context of IR-drop. An original algorithm is proposed allowing to perform an event-driven delay simulation of the logic Block Under Test (BUT) while taking into account the whole chip IR-drop impact on the simulated block. To do so, we develop accurate and efficient electrical models for the currents generated by the switching gates, the propagation of the current draw through the PDN and the gate delays. First, the pre-characterization process for the dynamic currents, static currents and gate delays is described to generate a gate library. Then, another pre-characterization procedure is suggested to estimate the current distribution through the resistive PDN model. Our models are implemented in a first version of the simulator by the University of Passau in the context of a project collaboration. In addition, the impact of the parasitic capacitive elements of the PDN is analyzed and a procedure to derive the current distribution in a resistive-capacitive PDN model is proposed.

Este trabalho propõe uma estratégia para projeto de circuitos VLSI operando em amplo ajuste de tensão e frequência (VFS), desde o regime em Near-threshold, onde uma tensão de VDD caracteriza-se por permitir o funcionamento do circuito com o mínimo dispêndio de energia por operação (MEP), até tensões nominais, dependendo da carga de trabalho exigida pela aplicação. Nesta dissertação é proposto o dimensionamento de transistores para três bibliotecas de células utilizando MOSFETs com tensões de limiar distintas: Regular-VT (RVT), High-VT (HVT) e Low-VT (LVT). Tais bibliotecas possuem cinco células combinacionais: INV, NAND, NOR, OAI21 e AOI22 em múltiplos strengths. A regra para dimensionamento dos transistores das células lógicas foi adaptada de trabalhos relacionados, e fundamenta-se na equalização dos tempos de subida e descida na saída de cada célula, objetivando à redução dos efeitos de variabilidade em baixas tensões de operação. Dois registradores também foram incluídos na biblioteca RVT e sua caracterização foi realizada considerando os parâmetros de processo CMOS 65 nm typical, fast e slow; nas temperaturas de operação de -40°C, 25°C e 125°C, e para tensões variando de 200 mV até 1,2V, para incluir a região de interesse, próxima ao MEP. Os experimentos foram realizados utilizando dez circuitos VLSI de teste: filtro digital notch, um núcleo compatível com o micro-controlador 8051, quatro circuitos combinacionais e quatro sequenciais do benchmark ISCAS. Em termos de economia de energia, operar no MEP resulta em uma redução média de 54,46% em relação ao regime de sub-limiar e até 99,01% quando comparado com a tensão nominal, para a temperatura de 25°C e processo típico. Em relação ao desempenho, operar em regime de VFS muito amplo propicia frequências máximas que variam de centenas de kHz até a faixa de centenas de MHz a GHz, para as temperaturas de -40°C e 25°C, e de MHz até GHz em 125°C. Os resultados desta dissertação, quando comparados a trabalhos relacionados, demonstraram, em média, redução de energia e ganho de desempenho de 24,1% e 152,68%, respectivamente, considerando os mesmos circuitos de teste, operando no ponto de mínima energia (MEP). / This work proposes a strategy for designing VLSI circuits to operate in a very-wide Voltage-Frequency Scaling (VFS) range , from the supply voltage at which the minimum energy per operation (MEP) is achieved, at the Near-Threshold regime, up to the nominal supply voltage for the processes, if so demanded by applications workload. This master thesis proposes the sizing of transistors for three library cells using MOSFETs with different threshold voltages: Regular-VT (RVT), High-VT (HVT), and Low-VT (LVT). These libraries have five combinational cells: INV, NAND, NOR, OAI21, and AOI22 with multiple strengths. The sizing rule for the transistors of the digital cells was an adapted version from related works and it is directly driven by requiring equal rise and fall times at the output for each cell in order to attenuate variability effects in the low supply voltage regime. Two registers were also included in the RVT library cell. This library cell was characterized for typical, fast, and slow processes conditions of a CMOS 65nm technology; for operation at -40ºC, 25ºC, and 125ºC temperatures, and for supply voltages varying from 200 mV up to 1.2V, to include the region of interest, for VDD near the MEP. Experiments were performed with ten VLSI circuit benchmarks: notch filter, 8051 compatible core, four combinational and four sequential ISCAS benchmark circuits. From the energy savings point of view, to operate in MEP results on average reduction of 54.46% and 99.01% when compared with the sub-threshold and nominal supply voltages, respectively. This analysis was performed for 25⁰C and typical process. When considered the performance, the very-wide VFS regime enables maximum operating frequencies varying from hundreds of kHz up to MHz/GHz at -40ºC and 25ºC, and from MHz up to GHz at 125ºC. This master thesis results, when compared with related works, showed on average an energy reduction and performance gain of 24.1% and 152.68%, respectively, for the same circuit benchmarks operating with VDD at the minimum energy point (MEP).

Este trabalho propõe uma estratégia para projeto de circuitos VLSI operando em amplo ajuste de tensão e frequência (VFS), desde o regime em Near-threshold, onde uma tensão de VDD caracteriza-se por permitir o funcionamento do circuito com o mínimo dispêndio de energia por operação (MEP), até tensões nominais, dependendo da carga de trabalho exigida pela aplicação. Nesta dissertação é proposto o dimensionamento de transistores para três bibliotecas de células utilizando MOSFETs com tensões de limiar distintas: Regular-VT (RVT), High-VT (HVT) e Low-VT (LVT). Tais bibliotecas possuem cinco células combinacionais: INV, NAND, NOR, OAI21 e AOI22 em múltiplos strengths. A regra para dimensionamento dos transistores das células lógicas foi adaptada de trabalhos relacionados, e fundamenta-se na equalização dos tempos de subida e descida na saída de cada célula, objetivando à redução dos efeitos de variabilidade em baixas tensões de operação. Dois registradores também foram incluídos na biblioteca RVT e sua caracterização foi realizada considerando os parâmetros de processo CMOS 65 nm typical, fast e slow; nas temperaturas de operação de -40°C, 25°C e 125°C, e para tensões variando de 200 mV até 1,2V, para incluir a região de interesse, próxima ao MEP. Os experimentos foram realizados utilizando dez circuitos VLSI de teste: filtro digital notch, um núcleo compatível com o micro-controlador 8051, quatro circuitos combinacionais e quatro sequenciais do benchmark ISCAS. Em termos de economia de energia, operar no MEP resulta em uma redução média de 54,46% em relação ao regime de sub-limiar e até 99,01% quando comparado com a tensão nominal, para a temperatura de 25°C e processo típico. Em relação ao desempenho, operar em regime de VFS muito amplo propicia frequências máximas que variam de centenas de kHz até a faixa de centenas de MHz a GHz, para as temperaturas de -40°C e 25°C, e de MHz até GHz em 125°C. Os resultados desta dissertação, quando comparados a trabalhos relacionados, demonstraram, em média, redução de energia e ganho de desempenho de 24,1% e 152,68%, respectivamente, considerando os mesmos circuitos de teste, operando no ponto de mínima energia (MEP). / This work proposes a strategy for designing VLSI circuits to operate in a very-wide Voltage-Frequency Scaling (VFS) range , from the supply voltage at which the minimum energy per operation (MEP) is achieved, at the Near-Threshold regime, up to the nominal supply voltage for the processes, if so demanded by applications workload. This master thesis proposes the sizing of transistors for three library cells using MOSFETs with different threshold voltages: Regular-VT (RVT), High-VT (HVT), and Low-VT (LVT). These libraries have five combinational cells: INV, NAND, NOR, OAI21, and AOI22 with multiple strengths. The sizing rule for the transistors of the digital cells was an adapted version from related works and it is directly driven by requiring equal rise and fall times at the output for each cell in order to attenuate variability effects in the low supply voltage regime. Two registers were also included in the RVT library cell. This library cell was characterized for typical, fast, and slow processes conditions of a CMOS 65nm technology; for operation at -40ºC, 25ºC, and 125ºC temperatures, and for supply voltages varying from 200 mV up to 1.2V, to include the region of interest, for VDD near the MEP. Experiments were performed with ten VLSI circuit benchmarks: notch filter, 8051 compatible core, four combinational and four sequential ISCAS benchmark circuits. From the energy savings point of view, to operate in MEP results on average reduction of 54.46% and 99.01% when compared with the sub-threshold and nominal supply voltages, respectively. This analysis was performed for 25⁰C and typical process. When considered the performance, the very-wide VFS regime enables maximum operating frequencies varying from hundreds of kHz up to MHz/GHz at -40ºC and 25ºC, and from MHz up to GHz at 125ºC. This master thesis results, when compared with related works, showed on average an energy reduction and performance gain of 24.1% and 152.68%, respectively, for the same circuit benchmarks operating with VDD at the minimum energy point (MEP).

Este trabalho propõe uma estratégia para projeto de circuitos VLSI operando em amplo ajuste de tensão e frequência (VFS), desde o regime em Near-threshold, onde uma tensão de VDD caracteriza-se por permitir o funcionamento do circuito com o mínimo dispêndio de energia por operação (MEP), até tensões nominais, dependendo da carga de trabalho exigida pela aplicação. Nesta dissertação é proposto o dimensionamento de transistores para três bibliotecas de células utilizando MOSFETs com tensões de limiar distintas: Regular-VT (RVT), High-VT (HVT) e Low-VT (LVT). Tais bibliotecas possuem cinco células combinacionais: INV, NAND, NOR, OAI21 e AOI22 em múltiplos strengths. A regra para dimensionamento dos transistores das células lógicas foi adaptada de trabalhos relacionados, e fundamenta-se na equalização dos tempos de subida e descida na saída de cada célula, objetivando à redução dos efeitos de variabilidade em baixas tensões de operação. Dois registradores também foram incluídos na biblioteca RVT e sua caracterização foi realizada considerando os parâmetros de processo CMOS 65 nm typical, fast e slow; nas temperaturas de operação de -40°C, 25°C e 125°C, e para tensões variando de 200 mV até 1,2V, para incluir a região de interesse, próxima ao MEP. Os experimentos foram realizados utilizando dez circuitos VLSI de teste: filtro digital notch, um núcleo compatível com o micro-controlador 8051, quatro circuitos combinacionais e quatro sequenciais do benchmark ISCAS. Em termos de economia de energia, operar no MEP resulta em uma redução média de 54,46% em relação ao regime de sub-limiar e até 99,01% quando comparado com a tensão nominal, para a temperatura de 25°C e processo típico. Em relação ao desempenho, operar em regime de VFS muito amplo propicia frequências máximas que variam de centenas de kHz até a faixa de centenas de MHz a GHz, para as temperaturas de -40°C e 25°C, e de MHz até GHz em 125°C. Os resultados desta dissertação, quando comparados a trabalhos relacionados, demonstraram, em média, redução de energia e ganho de desempenho de 24,1% e 152,68%, respectivamente, considerando os mesmos circuitos de teste, operando no ponto de mínima energia (MEP). / This work proposes a strategy for designing VLSI circuits to operate in a very-wide Voltage-Frequency Scaling (VFS) range , from the supply voltage at which the minimum energy per operation (MEP) is achieved, at the Near-Threshold regime, up to the nominal supply voltage for the processes, if so demanded by applications workload. This master thesis proposes the sizing of transistors for three library cells using MOSFETs with different threshold voltages: Regular-VT (RVT), High-VT (HVT), and Low-VT (LVT). These libraries have five combinational cells: INV, NAND, NOR, OAI21, and AOI22 with multiple strengths. The sizing rule for the transistors of the digital cells was an adapted version from related works and it is directly driven by requiring equal rise and fall times at the output for each cell in order to attenuate variability effects in the low supply voltage regime. Two registers were also included in the RVT library cell. This library cell was characterized for typical, fast, and slow processes conditions of a CMOS 65nm technology; for operation at -40ºC, 25ºC, and 125ºC temperatures, and for supply voltages varying from 200 mV up to 1.2V, to include the region of interest, for VDD near the MEP. Experiments were performed with ten VLSI circuit benchmarks: notch filter, 8051 compatible core, four combinational and four sequential ISCAS benchmark circuits. From the energy savings point of view, to operate in MEP results on average reduction of 54.46% and 99.01% when compared with the sub-threshold and nominal supply voltages, respectively. This analysis was performed for 25⁰C and typical process. When considered the performance, the very-wide VFS regime enables maximum operating frequencies varying from hundreds of kHz up to MHz/GHz at -40ºC and 25ºC, and from MHz up to GHz at 125ºC. This master thesis results, when compared with related works, showed on average an energy reduction and performance gain of 24.1% and 152.68%, respectively, for the same circuit benchmarks operating with VDD at the minimum energy point (MEP).

En la dècada actual, l'augment del consum energètic dels circuits integrats està tenint un impacte cada vegada més important en el disseny electrònic. Segons l'informe de la Semiconductor Industry Association de l'any 1997, es preveu que aquest impacte serà encara major en la propera dècada. En la bibliografia existeixen diversos treballs on es relaciona un consumo energètic elevat amb la degradació de les prestacions i la fiabilitat del xip. Per aquesta raó, el consum energètic ha estat incorporat com a un altre paràmetre a tenir en compte en el disseny dels circuits integrats. Es coneix com a energia de transició l'energia consumida per un circuit combinacional CMOS quan es produeix un canvi en les seves entrades. Una energia de transició excessivament elevada pot afectar a la fiabilitat del xip a través dels anomenats hot spots, i de l'electromigració. Altres efectes com el ground bouncing i la signal integrity degradation poden repercutir en les prestacions del circuit. La minimització de les degradacions esmentades anteriorment requereixen de la caracterització de l'energia de transició màxima durant la fase de disseny. A tal efecte, en aquesta tesi es proposen dues metodologies que permeten l'estimació de l'energia de transició màxima en circuits combinacionals CMOS. Donat que l'estimació del nivell màxim exacte es inviable en circuits a partir de mides mitjanes, es proposa el càlcul de dues cotes, una d'inferior i una altra de superior, que delimiten un interval de localització de l'esmentat nivell màxim. La tesi està estructurada en els següents capítols. En el capítol 1 es fa una introducció al tema investigat en aquesta tesi i es presenten els treballs existents que el tracten. En el capítol 2 s'introdueixen els models d'estimació de l'energia de transició emprats més habitualment a nivell lògic, que és el nivell de disseny considerat en aquesta tesi. Aquests models assumeixen que l'únic mecanisme de consum és la commutació de les capacitats paràsites del circuit. En els capítols 3 i 4 es tracta l'estimació de l'energia de transició màxima. Aquesta estimació es realitza a partir del càlcul de dues cotes properes, una superior i una altre inferior, a aquesta energia màxima. En el capítol 5 es presenta l'anàlisi del comportament de l'activitat ponderada front als models de retard estàtics. Finalment, en el capítol 6 s'aborden les conclusions generals de la tesis i el treball futur. / El consumo energético de los circuitos integrados es un factor cuyo impacto en el diseño electrónico ha crecido significativamente en la década actual. Según el informe de la Semiconductor Industry Association del año 1997, se prevé que este impacto será aún mayor en la próxima década. En la bibliografía existen diversos trabajos donde se relaciona un consumo energético elevado con la degradación de las prestaciones y la fiabilidad del chip. Por esta razón, el consumo energético ha sido incorporado como otro parámetro a tener en cuenta en el diseño de los circuitos integrados. Se conoce como energía de transición la energía consumida por un circuito combinacional CMOS cuando se produce un cambio en las entradas del mismo. Una energía de transición excesivamente elevada puede afectar a la fiabilidad del chip a través de los hot spots, de la electromigración. Otros efectos como el ground bouncing y la signal integrity degradation pueden repercutir en las prestaciones del circuito. La minimización de las degradaciones mencionadas anteriormente requiere de la caracterización de la energía de transición máxima durante la fase de diseño. A este efecto, se propone en esta tesis dos metodologías que permiten la estimación de la energía de transición máxima en circuitos combinacionales CMOS. Dado que la estimación del nivel máximo exacto es inviable en circuitos a partir de tamaños medios, se propone el cálculo de dos cotas, una de inferior y otra de superior, que delimiten un intervalo de localización de dicho nivel máximo. La tesis está estructurada en los siguientes capítulos. En el capítulo 1 se presenta una introducción al tema investigado en esta tesis y se resumen los trabajos existentes más importantes. En el capítulo 2 se introducen los modelos de estimación de la energía de transición más comúnmente utilizados a nivel lógico, que es el nivel de diseño considerado en esta tesis. Estos modelos asumen que el único mecanismo de consumo es la conmutación de las capacidades parásitas del circuito. En los capítulos 3 y 4 se aborda la estimación de la energía de transición máxima. Esta estimación se realiza a partir del cálculo de dos cotas cercanas, una superior y una inferior, a esta energía máxima. En el capítulo 5 se presenta el análisis del comportamiento de la actividad ponderada frente a los modelos de retardo estáticos. Finalmente, en el capítulo 6 se presentan las conclusiones generales de la tesis y el trabajo futuro. / The importance of the energy consumption on the design of electronic circuits has increased significantly during the last decade. According to the report of the Semiconductor Industry Association, of 1997, the impact in the next decade will be even greater. In the bibliography several works exist relating to the high energy consumption with the degradation of the reliability and performance of the xip. For this reason, the energy consumption has been included as another parameter to take into account during the design of integrated circuits. It is known as transition energy, the energy consumed by a CMOS combinational circuit when its inputs change their value. Excessively high transition energy may affect the reliability of the chip through the generation of hot spots and electromigration. Other effects such as ground bouncing and signal integrity degradation may reduce the performance of the circuit. In order to minimize the previously detected bad effects it is useful to characterize the maximum transition energy, during the design phase. To this objective, this thesis presents two methodologies that allow for the estimation of the maximum transition energy in CMOS combinational circuits. Given that the estimation of the maximum level is only attainable for medium size circuits, it is proposed the calculation of bounds (higher and lower) delimiting the interval where the maximum level is located. The thesis is divided into the following chapters. In chapter 1 an introduction to the topic and a review of the previous works related to this research domain is given. In chapter 2 the models most extended for the estimation of the transition energy are presented. These models are mainly used at logic level which is the level assumed in this thesis. They assume that the switching of the parasitic capacitances is the only mechanism producing energy consumption. In chapters 3 and 4 the estimation of the maximum transition energy is considered. This estimation is made from the calculation of an upper and lower bound to this maximum transition energy. In chapter 5 the analysis of the switching activity is made for different static delay models. Finally, in chapter 6 the general conclusions of the thesis and future work are discussed.

L’émergence des circuits complexes numériques, ou System-On-Chip (SOC), pose notamment la problématique de la consommation énergétique. Parmi les blocs fonctionnels significatifs à ce titre, apparaissent les mémoires et en particulier les mémoires statiques (SRAM). La maîtrise de la consommation énergétique d’une mémoire SRAM inclue la capacité à rendre la mémoire fonctionnelle sous très faible tension d’alimentation, avec un objectif agressif de 300 mV (inférieur à la tension de seuil des transistors standard CMOS). Dans ce contexte, les travaux de thèse ont concerné la proposition d’un point mémoire SRAM suffisamment performant sous très faible tension d’alimentation et pour les nœuds technologiques avancés (CMOS bulk 28nm et FDSOI 28nm). Une analyse comparative des architectures proposées dans l’état de l’art a permis d’élaborer deux points mémoire à 10 transistors avec de très faibles impacts de courant de fuite. Outre une segmentation des ports de lecture, les propositions reposent sur l’utilisation de périphéries adaptées synchrones avec notamment une solution nouvelle de réplication, un amplificateur de lecture de données en mode tension et l’utilisation d’une polarisation dynamique arrière du caisson SOI (Body Bias). Des validations expérimentales s’appuient sur des circuits en technologies avancées. Enfin, une mémoire complète de 32kb (1024x32) a été soumise à fabrication en 28 FDSOI. Ce circuit embarque une solution de test (BIST) capable de fonctionner sous 300mV d’alimentation. Après une introduction générale, le 2ème chapitre du manuscrit décrit l’état de l’art. Le chapitre 3 présente les nouveaux points mémoire. Le 4ème chapitre décrit l’amplificateur de lecture avec la solution de réplication. Le chapitre 5 présente l’architecture d’une mémoire ultra basse tension ainsi que le circuit de test embarqué. Les travaux ont donné lieu au dépôt de 4 propositions de brevet, deux conférences internationales, un article de journal international est accepté et un autre vient d’être soumis. / Emergence of large Systems-On-Chip introduces the challenge of power management. Of the various embedded blocks, static random access memories (SRAM) constitute the angrier contributors to power consumption. Scaling down the power supply is one way to act positively on power consumption. One aggressive target is to enable the operation of SRAMs at Ultra-Low-Voltage, i.e. as low as 300 mV (lower than the threshold voltage of standard CMOS transistors). The present work concerned the proposal of SRAM bitcells able to operate at ULV and for advanced technology nodes (either CMOS bulk 28 nm or FDSOI 28 nm). The benchmarking of published architectures as state-of-the-art has led to propose two flavors of 10-transitor bitcells, solving the limitations due to leakage current and parasitic power consumption. Segmented read-ports have been used along with the required synchronous peripheral circuitry including original replica assistance, a dedicated unbalanced sense amplifier for ULV operation and dynamic forward back-biasing of SOI boxes. Experimental test chips are provided in previously mentioned technologies. A complete memory cut of 32 kbits (1024x32) has been designed with an embedded BIST block, able to operate at ULV. After a general introduction, the manuscript proposes the state-of-the-art in chapter two. The new 10T bitcells are presented in chapter 3. The sense amplifier along with the replica assistance is the core of chapter 4. The memory cut in FDSOI 28 nm is detailed in chapter 5. Results of the PhD have been disseminated with 4 patent proposals, 2 papers in international conferences, a first paper accepted in an international journal and a second but only submitted paper in an international journal.