The integration of image sensors and high performance processors into embedded systems enabled the development of intelligent vision systems. In this thesis, we developed an active autonomous system to be used for surveillance applications. The proposed system detects a single moving object in the field of view automatically and tracks it in a wide area by controlling the pan-tilt-zoom features of the camera. The system can also go to an alarm state to warn the user. The processing unit of the system is a Texas Instruments DM642 Evaluation Module which is a low-cost high performance video &amp / imaging development platform designed to develop and evaluate video based applications.

Based on sliding-mode control theory, this thesis proposes an integrated design of robust speed controller and quantized current regulator to achieve the control of inverter for BLDC motor. Moreover, using Digital Signal Processor (DSP) as well as the proposed inverter technology as the control kernel, a fully digital drive module of Brushless DC motor (BLDC) is robustly designed to achieve the high-performance speed control. Under the influence of system disturbances, the designed drive module can obtain a good tracking response for speed and current control. According to the simulation and experimental studies, the proposed hybrid control strategy can simultaneously achieve the objective for the speed and current control of BLDC motor. Compared with traditional pulse-width modulation (PWM) based PID control, the better speed control performance can be conducted by the provided approach.

Technology is integrated into daily life more than before as it evolves through communication area. In the past, it started with audio devices that help us to communicate while far between two ends of communication line. Nowadays visual communication comes in front considering the communication technology. This became possible with the improvement in the compression techniques of visual data and increasing speed, optimized architecture of the new family processors. These type processors are named as Digital Signal Processors (DSP&rsquo / s). Texas Instruments TMS320C6000 Digital Signal Processor family offers one of the fastest DSP core in the market. TMS320C64x sub-family processors are newly developed under the TMS320C6000 family to overcome disadvantages of its predecessor family TMS320C62x. TMS320C64x family has optimized architecture for packed data processing, improved data paths and functional units,improved memory architecture and increased speed. These capabilities make this family of processors good candidate for real-time video processing applications. Advantages of this core are used for implementing newly established H.264 Recommendation. Highly optimizing C Compiler of TMS320C64x enabled fast running implementation of encoder blocks that bring heavy computational load to encoder. Such as fast implementation of Motion Estimation, Transform, Entropy Coding became possible. Simplified Densely Centered Uniform-P Search algorithm is used for fast estimation of motion vectors. Time taking parts enhanced to improve the performance of the encoder.

abstract: With the increasing penetration of Photovoltaic inverters, there is a necessity for recent PV inverters to have smart grid support features for increased power system reliability and security. The grid support features include voltage support, active and reactive power control. These support features mean that inverters should have bidirectional power and communication capabilities. The inverter should be able to communicate with the grid utility and other inverter modules. This thesis studies the real time simulation of smart inverters using PLECS Real Time Box. The real time simulation is performed as a Controller Hardware in the Loop (CHIL) real time simulation. In this thesis, the power stage of the smart inverter is emulated in the PLECS Real Time Box and the controller stage of the inverter is programmed in the Digital Signal Processor (DSP) connected to the real time box. The power stage emulated in the real time box and the controller implemented in the DSP form a closed loop smart inverter. This smart inverter, with power stage and controller together, is then connected to an OPAL-RT simulator which emulates the power distribution system of the Arizona State University Poly campus. The smart inverter then sends and receives commands to supply power and support the grid. The results of the smart inverter with the PLECS Real time box and the smart inverter connected to an emulated distribution system are discussed under various conditions based on the commands received by the smart inverter. / Dissertation/Thesis / Masters Thesis Electrical Engineering 2017

Made available in DSpace on 2014-06-11T19:22:31Z (GMT). No. of bitstreams: 0 Previous issue date: 2007-06-15Bitstream added on 2014-06-13T19:08:03Z : No. of bitstreams: 1 martinhon_g_me_ilha.pdf: 1559279 bytes, checksum: 7e975933281fbe9aec5c7a3556631af8 (MD5) / Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES) / A estimação do tempo de atraso entre dois sinais de ultra-som é uma tarefa muito comum e importante em diversas aplicações, como em sistemas de posicionamento para medição de distâncias, medidores de espessura em ensaios não-destrutivos, células de medição de propriedades de materiais, entre outros. Em algumas aplicações há necessidade de elevada acurácia e precisão na determinação do tempo de atraso, que dependem de diversos parâmetros do transdutor, de sua excitação e do meio em que a onda se propaga, além do método de estimação e representação numérica. Neste trabalho são avaliados três estimadores de tempo de atraso, com implementações em ponto-fixo e ponto-flutuante: correlação cruzada com interpolação parabólica, transformada de Hilbert da correlação e envoltória do sinal analítico. Os estimadores são avaliados em MATLAB, em ponto-flutuante, com sinais sintetizados e com sinais reais obtidos em laboratório, e em ponto-fixo, usando um processador digital de sinais TMS320VC5416, da Texas Instruments. São explorados parâmetros como freqüência central do transdutor, freqüência de amostragem, largura de banda, relação sinal-ruído e atenuação do meio. O desempenho dos métodos é comparado por meio dos erros médios e desvios-padrão das medidas / Time-delay estimation between two ultrasonic signals is a very common and important task in several applications, such as distance measurement in positioning systems, thickness measurement in nondestructive testing, measurement cells of materials properties, among others. Some applications require high accuracy and precision on the determination of the time-delay, which depend on several transducer parameters, excitation and medium of propagation, as well as the estimation method and numerical representation. In this work, three time-delay estimators are evaluated, with fixed- and floating-point implementations: cross-correlation with parabolic interpolation, Hilbert transform of correlation and analytic signal envelope. The estimators are evaluated in MATLAB with floating-point representation, using synthesized signals and real signals acquired in laboratory, and in fixed-point using a Texas Instruments TMS320VC5416 digital signal processor. Parameters as transducer central frequency, sampling frequency, bandwidth, signal-to-noise ratio and medium attenuation are considered. The performances of the methods are compared by means of errors (or bias) and standard deviations

Classical Molecular Dynamics simulation (MD) models the interactions of thousands to millions of particles through the iterative application of basic Physics. MD is one of the core methods in High Performance Computing (HPC). While MD is critical to many high-profile applications, e.g. drug discovery and design, it suffers from the strong scaling problem, that is, while large computer systems can efficiently model large ensembles of particles, it is extremely challenging for {\it any} computer system to increase the timescale, even for small ensembles. This strong scaling problem can be mitigated with low-latency, direct communication. Of all Commercial Off the Shelf (COTS) Integrated Circuits (ICs), Field Programmable Gate Arrays (FPGAs) are the computational component uniquely applicable here: they have unmatched parallel communication capability both within the chip and externally to couple clusters of FPGAs. This thesis focuses on the acceleration of the long range (LR) force, the part of MD most difficult to scale, by using FPGAs. This thesis first optimizes LR acceleration on a single-FPGA to eliminate the amount of on-chip communication required to complete a single LR computation iteration while maintaining as much parallelism as possible. This is achieved by designing around application specific memory architectures. Doing so introduces data movement issues overcome by pipelined, toroidal-shift multiplexing (MUXing) and pipelined staggering of memory access subsets. This design is then evaluated comprehensively and comparatively, deriving equations for performance and resource consumption and drawing metrics from previously developed LR hardware designs. Using this single-FPGA LR architecture as a base, FPGA network strategies to compute the LR portion of larger sized MD problems are then theorized and analyzed.

著者名別形の記述を修正（2022-04-21） / 京都大学 / 0048 / 新制・課程博士 / 博士(工学) / 甲第16850号 / 工博第3571号 / 新制||工||1540(附属図書館) / 29525 / 京都大学大学院工学研究科材料工学専攻 / (主査)教授 河合 潤, 教授 酒井 明, 教授 大塚 浩二 / 学位規則第4条第1項該当 / Doctor of Philosophy (Engineering) / Kyoto University / DFAM

Modern handheld devices rely on specialized hardware for evaluating machine learning algorithms. This thesis investigates the feasibility of using the digital signal processor, a part of the modem of the device, as an alternative to this specialized hardware. Memory management techniques and implementations for evaluating the machine learning primitives convolutional, max-pooling and fully connected layers are proposed. The implementations are evaluated based on to what degree they utilize available hardware units. New instructions for packing data and facilitating instruction pipelining are suggested and evaluated. The results show that convolutional and fully connected layers are well-suited to the processor used. The aptness of the convolutional layer is subject to the kernel being applied with a stride of 1 as larger strides cause the hardware usage to plummet. Max-pooling layers, while not ill-suited, are the most limited in terms of hardware usage. The proposed instructions are shown to have positive effects on the throughput of the implementations.

Modern public-key cryptography relies extensively on modular multiplication with long operands. We investigate the opportunities to optimize this operation in a heterogeneous multiprocessing platform such as TI OMAP3530. By migrating the long operand modular multiplication from a general-purpose ARM Cortex A8 to a specialized C64x+ VLIW DSP, we are able to exploit the XOR-Multiply instruction and the inherent parallelism of the DSP. The proposed multiplication utilizes Multi-Precision Binary Polynomial Multiplication with Unbalanced Exponent Modular Reduction. The resulting DSP implementation performs a GF(2^233) multiplication in less than 1.31us, which is over a seven times speed up when compared with the ARM implementation on the same chip. We present several strategies for different field sizes and field polynomials, and show that a 360MHz DSP easily outperforms the 500MHz ARM. / Master of Science

International Telemetering Conference Proceedings / October 27-30, 1997 / Riviera Hotel and Convention Center, Las Vegas, Nevada / Telemetry & Instrumentation, in conjunction with NASA’s Kennedy Space Center, has developed a commercial, intelligent, data acquisition module that performs all functions associated with acquiring and digitizing a transducer measurement. These functions include transducer excitation, signal gain and anti-aliasing filtering, A/D conversion, linearization and digital filtering, and sample rate decimation. The functions are programmable and are set up from information stored in a local Transducer Electronic Data Sheet (TEDS). In addition, the module performs continuous self-calibration and self-test to maintain 0.01% accuracy over its entire operating temperature range for periods of one year without manual recalibration. The module operates in conjunction with a VME-based data acquisition system.