In the current transmission systems, the transmission capacity is still not enough. The information bandwidth of the optical fiber communication system is limited by the optical amplifier bandwidth, and more efficient use of the bandwidth is a very important issue. Therefore, the amplitude and phase shift keying (APSK) is one attractive method of multi-bit per symbol modulation scheme to improve the spectral efficiency, and it can effectively increase the transmission capacity. To improve the capacity and the spectral efficiency, the advanced modulation format is effective, and the coherent detection scheme is also effective. However, an optical phase-locked loop (PLL) to lock the local oscillator (LO) phase and the signal phase required for the homodyne detection is still difficult to realize and it makes the receiver circuit complicated. Using the digital coherent receiver, the optical carrier phase information can be recovered by means of the digital signal processing (DSP), and this scheme enables to eliminate the optical PLL circuit by the phase estimation algorithm through the DSP. The stored data can be offline processed by using the MATLAB program. This master thesis is focusing on studying the transmission performance of the APSK format using the DSP in the digital coherent receiver. 497km transmission experiment has been conducted. Subsequently, the stored data are offline processed by the algorithms of the DSP. Then, the APSK performances between back-to-back and 497km transmission are compared.

This study aims to design a Shunt Semi-Active Power Factor Correction Circuits , which can be applied to high power circuit by low switching frequency. The designed circuit can avoid power loss working with high switching frequency when using the method of active power factor correction .The experimental configuration based on DSP is applied to a compressor of air conditioner with varied load. The simulation check the developed circuit using Ispice . Both of the experimental and simulation results have guaranteed the derived configuration reach the expected goals.

The coherent optical fiber communication technology is attracting significant attentions in the world, because it can realize the spectrally efficient transmission system. One major difference between 1980¡¦s and the latest coherent technology is the utilization of the digital signal processing (DSP). In 1980¡¦s the optical phase locked loop (OPLL) was required to realize the homodyne detection, and it was significantly difficult to realize. The latest coherent technology utilizes the DSP in place of the OPLL to realize the homodyne detection, and it is much easier than the OPLL. The real-time realization of the DSP is still a problem. Because the DSP uses software to process the signal, it needs an extreme calculation power for the high-speed communication system. People always utilize the field programmable gate array (FPGA) to realize the real-time DSP, but the cost of the FPGA is too expensive for the commercial system at this moment. This master thesis intend to utilize commercially available personal computer (PC) contained a GPU calculation board to replace FPGA. It can reduce the cost of the coherent receiver. Also, this receiver is defined by the software rather than the hardware. It means that we can realize a flexible receiver defined by the software.

This thesis presented a sensor-less permanent magnet synchronous motor (PMSM) driver for controlling air-conditioner rotary compressor speed. In this thesis, a quasi-sine pulse-width modulation (PWM) driving method was proposed. Furthermore, the current feedback control scheme and rotor magnet pole position detection were included. The system structure was implemented by using a digital signal processing (DSP) platform. The proposed driving scheme was compared with the square-wave driving without current feedback and six-step square-wave driving method with current feedback. Moreover, the passive and shunt semi-active power factor correction (PFC) technique were researched for the air-conditioner application. Experimental results demonstrated that the system power factor could be improved by the proposed shunt semi-active PFC method. Besides, the proposed sensor-less quasi-sine PWM driving method implemented in an air-conditioner compressor driver was capable of reducing the magnitude of rotational speed ripples, compressor vibration, and system power consumption.

The reluctance torque of switched reluctance motor could drive the rotor directly. Rotor doesn¡¦t need to be made from permanent magnet and the demagnetization and heat emission problems can be avoided. There are also a lot of advantages, such as the low cost, high efficiency, high stability and high hot emission, make it very attractive to the engineers and researchers. The dual-flange-pole rotor structure will induce non-linear magnetic filed in the air gap between armature and rotor, so the reluctance torque is not easy to handle. The switched reluctance motor is considered hard to control at the early stages of development. In recently years, with the rapid improvement of power electronic devices and microprocessor chips, the engineers and researchers pay more attentions to overcome the difficulties encountered in both the software and hardware step by step. It can now exert the motor¡¦s capability to contend with the inductor motor and the alternating current motor. Furthermore, it is more advantageous than others in the high energy density, high temperature and adverse circumstances. It has obviously caught caused the industry¡¦s attention and the academia's research interests. The work of this is to design and develop a drive system for the switched reluctance motor drive system by using the 32-bit floating point Digital Signal Processor, and operate it in coordination with the peripheral circuits. Finally, the study will integrate the graph control programming to design a monitoring and control system with Man-Machinery Interface (MMI) for monitoring voltage, current and speed of the switched reluctance motor drive system.

Due to the differences in batteries of a series-connected battery bank, the restored capacity in each battery may not be the same when being charged. In order to extend battery cycle life, the charger for the battery bank must have the capability of charging equalization. This thesis proposes a non-dissipative balance charging circuit based on buck-boost topology for a series-connected battery bank. Each battery in a battery bank is associated with a buck-boost converter. This topology can efficiently alleviate the unbalance of charge among batteries by taking off the charge from the affluently charged batteries and then allotting to those insufficient ones. To accomplish this complicated and accurate control, a digital signal processor (DSP) with sensors and interface circuits is adopted. It monitors the variations of battery voltages, activates the associated buck-boost converter, and adjusts the duty ratio of the converter to regulate the energy to be released. In virtue of the adoption of digital control kernel, the control circuit can be simple and the control flexibility can be favored. A battery bank with four series connected lead-acid batteries is used for illustrating the operating behavior and describing the operation modes of the balance charging circuit. The results of experiments convincingly advocate the applicability of the proposed approach.

The design of this thesis intends to present that 120¢X Communication and Flux-Weakening Control techniques can be successfully applied to a Digital Signal Processor (DSP) together with the hardware structure of an inverter. Experimental results are shown that utilizing IPM Motor as Drive Motor of Electric Vehicle, 120¢X Communication techniques can reduce ripple torque and maintain the stability of output torque. Furthermore, through Phase advanced control motor, it enables a higher output torque during the mid-lower speed. Using Flux-Weakening Control helps motor from higher output speed to the highest output speed. Moreover, the security of motor driver can be enhanced by designing circuit, which prevents over voltage. The function of motor driver will be better due to the decreased hardware size and increased accuracy that are the advantage of writing DSP scripts to analyze rotor speed.

The design and implementation of the digital signal processing (DSP) based on a brushless DC (BLDC) motor sensorless driver with Sine PWM. Because of dispensable power consumption problems generated by closed-loop speed control methods with speed estimation signal feedback are adopted for improvement. In addition, current feedback is added to the driver for the sake of increasing efficiency. Then, sine wave closes 30¢X, 15¢X, and 8¢X to comparing the improvements for efficiency. Experimental results from a laboratory prototype are shown to verify the feasibility of the proposed scheme. The laboratory results show that current feedback and sine wave closed 8¢X have high efficiency.

<p>This Master thesis describes the benchmarking of a DSP processor. Benchmarking means measuring the performance in some way. In this report, we have focused on the number of instruction cycles needed to execute certain algorithms. The algorithms we have used in the benchmark are all very common in signal processing today. </p><p>The results we have reached in this thesis have been compared to benchmarks for other processors, performed by Berkeley Design Technology, Inc. </p><p>The algorithms were programmed in assembly code and then executed on the instruction set simulator. After that, we proposed changes to the instruction set, with the aim to reduce the execution time for the algorithms. </p><p>The results from the benchmark show that our processor is at the same level as the ones tested by BDTI. Probably would a more experienced programmer be able to reduce the cycle count even more, especially for some of the more complex benchmarks.</p>

This report presents improved architecture designs and implementations for a fused floating-point add-subtract unit. The fused floating-point add-subtract unit is useful for DSP applications such as FFT and DCT butterfly operations. To improve the performance of the fused floating-point add-subtract unit, the dual path algorithm and pipelining technique are applied. The proposed designs are implemented for both single and double precision and synthesized with a 45nm standard-cell library. The fused floating-point add-subtract unit saves 40% of the area and power consumption and the dual path fused floating-point add-subtract unit reduces the latency by 30% compared to the traditional discrete floating-point add-subtract unit. By combining fused operation and the dual path design, the proposed floating-point add-subtract unit achieves low area, low power consumption and high speed. Based on the data flow analysis, the proposed fused floating-point add-subtract unit is split into two pipeline stages. Since the latencies of two pipeline stages are fairly well balanced the throughput of the entire logic is increased by 80% compared to the non-pipelined implementation. / text