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Modern public-key cryptography relies extensively on modular multiplication with long operands. We investigate the opportunities to optimize this operation in a heterogeneous multiprocessing platform such as TI OMAP3530. By migrating the long operand modular multiplication from a general-purpose ARM Cortex A8 to a specialized C64x+ VLIW DSP, we are able to exploit the XOR-Multiply instruction and the inherent parallelism of the DSP. The proposed multiplication utilizes Multi-Precision Binary Polynomial Multiplication with Unbalanced Exponent Modular Reduction. The resulting DSP implementation performs a GF(2^233) multiplication in less than 1.31us, which is over a seven times speed up when compared with the ARM implementation on the same chip. We present several strategies for different field sizes and field polynomials, and show that a 360MHz DSP easily outperforms the 500MHz ARM. / Master of Science

This paper outlines the design of a high-precision graphic audio equalizer with digital filters in parallel, along with its implementation in MATLAB App Designer. The equalizer is comprised of 31 bands separated with a one-third octave frequency ratio, and its frequency response is controlled by 63 filters. Furthermore, the application can process audio signals, in real time, recorded by microphone and from audio files. While processing, it displays an FFT plot of the output sound, also in real time, equipped with a knob by which the refreshing pace can be adjusted. The actual frequency response proved to match the desired one accurately, but the matching is computationally demanding for the computer. An even higher accuracy would entail a computational complexity beyond the power of ordinary computers, and was thus concluded to be inappropriate. As a result, the final application manages to provide most laptops with both high precision and proper functionality.

This thesis describes the theoretical development, design, and implementation of a novel measurement system, called a Sampling Swept Time Delay Short Pulse (SSTDSP) wireless channel sounder, capable of real time in field performance characterization of high speed fixed wireless links. The SSTDSP sounder has been designed to provide vital performance metrics for fixed point high data rate applications in the 28 GHz LMDS band at a fraction of the cost and complexity of existing wideband channel sounders. The SSTDSP sounder monitors the behavior of the LMDS channel by sampling the impulse response of the channel in real time. This digitized impulse response is used to assemble a power delay profile and render real-time channel performance metrics such as the mean excess delay, RMS delay spread, maximum excess delay for a given multipath threshold, and coherence bandwidth. The SSTDSP sounder is capable of recording these metrics through three modes of operation - continuous channel monitoring, single instant channel snapshot, or data logging. Swept time delay time dilation processing is combined with precise sample and hold gating to reduce the analog to digital converter sampling rate required to digitize the nanosecond short pulses from 2 Gsps to 1 Msps, while retaining the required effective Nyquist sampling rate of 2 Gsps. This dramatically reduces the memory, digital signal processing, and data logging storage requirements as well as the overall cost of the sounder system. The thesis presents the theory behind channel sounding and discusses whether there is a "bounce path" available to LMDS. Several existing channel sounding methods are compared for this application. A number of specific design and performance criteria from each of these methods are synthesized to produce the Sampling Swept Time Delay Short Pulse Sounder architecture. The design and implementation process used to realize the SSTDSP sounder is presented, including a system overview, module details, and algorithm development details. A calibration and measurement test procedure is outlined and system verification results are presented. Current work in progress on the test platform and future improvements to the modular system are outlined, as well as conclusions and future implications of the system. / Master of Science

International Telemetering Conference Proceedings / October 25-28, 1999 / Riviera Hotel and Convention Center, Las Vegas, Nevada / L-3 Communications Telemetry & Instrumentation (L-3 T&I) has developed an advanced IBM PC-AT Telemetry, Tracking, and Commanding (TT&C) SATCOM system based on the utilization of Field Programmable Gate Array / Digital Signal Processing (FPGA/DSP) microprocessors. This system includes up-link, down-link, and range processing sections. Physically, the system consists of one IF Transceiver and two or more FPGA/DSP microprocessor boards called Advanced Processing Microprocessors (APMs). The form factor of these PWBs is compliant with full length, full height IBM PC PCI bus cards. This paper describes the features and functionality of an advanced Telemetry, Tracking, and Commanding Processing System (TT&CPS) based on the implementation of FPGA and DSP microprocessors. The high-level functional attributes of the TT&CPS are depicted in Figure 1. There are four main functional blocks: the IF Transceiver, the Down-Link Processing Section, the Up-Link Processing Section, and the Range Processor. The analog/IF circuitry in the IF Transceiver card interfaces between the 68–72 MHz (70 MHz, nominal) IF I/O signals and the Up-Link and Down-Link Processing Section's DSP equipment. The down-link portion of the IF Transceiver card has two user-selected input ports. From the selected input, the signal is processed through selectable bandwidth limiting, gain control, Doppler correction (optional), quadrature down-conversion to zero hertz (baseband), selectable baseband filtering, and precision Analog-to-Digital (A/D) conversion. The up-link portion of the IF Transceiver card takes I/Q digital data from the APM performing the up-link processing functions. This baseband I/Q digital data is Digital-to-Analog (D/A) converted, filtered, quadrature up-converted to 68–72 MHz, up-link Doppler corrected (optional), output level detected and level controlled, and sent to a two-position output selector switch. The down-link portion of the TT&CPS provides main carrier linear PM or BPSK or QPSK demodulation and can also, in composite linear PM demodulation mode, receive and demodulate FSK and/or BPSK subcarriers and ranging signals. The demodulators use symbol timing loops and bit decision circuits (matched filters) to perform the bit synchronization function. Several decoding algorithms, including differential, de-interleaving, Viterbi, and Reed-Solomon, are available for the down-link telemetry. Command format checking and CRC status is also available on FSK-demodulated data. Direct carrier BPSK/QPSK demodulation has decoding and frame synchronization capabilities. Because of the modular construction of the firmware and the use of FPGAs and DSPs, the system can be loaded with only the functions in use, lowering initial setup time while increasing overall system capability. To support a particular function, the card is downloaded with an “image,” which programs the FPGAs and DSPs at initialization. The user can change configurations by simply downloading a new set of instructions to the FPGA/DSP on the fly to keep the ground station running with minimal downtime. The flexibility of the design minimizes spare board costs, while achieving greater programmability at the end-user location.

International Telemetering Conference Proceedings / October 23-26, 2000 / Town & Country Hotel and Conference Center, San Diego, California / Range to an orbiting satellite from a ground reference point (ground station) can be determined by measuring the round trip time for a waveform transmitted to the satellite and returned to the ground station (Turnaround Ranging) and more recently by using the Global Positioning System (GPS). This paper first summarizes and compares the two approaches. The paper then describes and analyzes a new turn-around ranging system which uses a flexible ranging waveform that provides spectral compatibility with existing Military, NASA, and Commercial satellite uplink/downlink signals.

International Telemetering Conference Proceedings / October 27-30, 1997 / Riviera Hotel and Convention Center, Las Vegas, Nevada / Telemetry & Instrumentation, in conjunction with NASA’s Kennedy Space Center, has developed a commercial, intelligent, data acquisition module that performs all functions associated with acquiring and digitizing a transducer measurement. These functions include transducer excitation, signal gain and anti-aliasing filtering, A/D conversion, linearization and digital filtering, and sample rate decimation. The functions are programmable and are set up from information stored in a local Transducer Electronic Data Sheet (TEDS). In addition, the module performs continuous self-calibration and self-test to maintain 0.01% accuracy over its entire operating temperature range for periods of one year without manual recalibration. The module operates in conjunction with a VME-based data acquisition system.

Speeding up addition is the key to faster digital signal processing (DSP). This can be achieved by exploiting the properties of redundant number systems. Their expanded symbol (digit) alphabet gives them multiple representations for most values. Utilising redundant representations at the output of an adder permits addition to be performed without carry-propagation, yielding fast, constant time performance irrespective of the word length. A resource efficient implementation of this fast adder structure is developed that re-purposes the fast carry logic of low-cost field programmable gate arrays (FPGAs). Experiments confirm constant time addition and show that it outperforms binary ripple carry addition at word lengths of greater than 44 bits in a Xilinx Spartan 3 FPGA and 24 bits in an Altera Cyclone III FPGA. Redundancy also provides other properties that can be exploited for performance gain. Some redundant representations will have more zero-symbols than others. These maximise the opportunities to exploit the multiplicative absorbing and additive identity properties of zero that when exercised reduce superfluous calculations. A serial recoding algorithm is developed that generates a redundant representation for a specified value with as few nonzero symbols as possible. Unlike previously published methods, it accepts a wide specification of number systems including those with irregularly spaced symbol alphabets. A Markov analysis and analysis of the elementary cycles in the formulated state machine provides average and worst case measures for the tested number system. Typically, the average number of non-zero symbols is less than a third and the worst case is less than a half. Further to the increase in zero-symbols, zero-dominance is proposed as a new property of redundant number representations. It promotes a set of representations that have uniquely positioned zero-symbols, in a Pareto-optimal sense. This set covers all representations of a value and is used to select representations to optimise the calculation of a dot-product. The dot-product or vector-multiply is a fundamental operation in DSP, since it is employed in filtering, correlation and convolution. The nonzero partial products can be packed together, substantially reducing the calculation time. The application of redundant number systems provides a two-fold benefit. Firstly, the number of nonzero partial products is reduced. Secondly, a novel opportunity is identified to use the representations in the zero-dominant set to optimise the packing further, gaining an extra 18% improvement. An implementation of the proposed dot-product with partial product packing is developed for a Cyclone II FPGA. It outperforms a quad-multiplier binary implementation in throughput by 50% . Redundant number systems excel at increasing performance in particular DSP subsystems, those that are numerically intensive and consist of considerable accumulation. The conversion back to a binary result is the performance bottleneck in the DSP algorithm, taking a time proportional to a binary adder. Therefore, redundant number systems are best utilised when this conversion cost can be amortised over many fast redundant additions, which is typical in many DSP and communications applications.

This thesis reports on new music technology research which investigates the use of cellular automata (CA) for the digital synthesis of dynamic sounds. The research addresses the problem of the sound design limitations of synthesis techniques based on CA. These limitations fundamentally stem from the unpredictable and autonomous nature of these computational models. Therefore, the aim of this thesis is to develop a sound synthesis technique based on CA capable of allowing a sound design process. A critical analysis of previous research in this area will be presented in order to justify that this problem has not been previously solved. Also, it will be discussed why this problem is worthwhile to solve. In order to achieve such aim, a novel approach is proposed which considers the output of CA as digital signals and uses DSP procedures to analyse them. This approach opens a large variety of possibilities for better understanding the self-organization process of CA with a view to identifying not only mapping possibilities for making the synthesis of sounds possible, but also control possibilities which enable a sound design process. As a result of this approach, this thesis presents a technique called Histogram Mapping Synthesis (HMS), which is based on the statistical analysis of CA evolutions by histogram measurements. HMS will be studied with four different automatons, and a considerable number of control mechanisms will be presented. These will show that HMS enables a reasonable sound design process. With these control mechanisms it is possible to design and produce in a predictable and controllable manner a variety of timbres. Some of these timbres are imitations of sounds produced by acoustic means and others are novel. All the sounds obtained present dynamic features and many of them, including some of those that are novel, retain important characteristics of sounds produced by acoustic means.

The upcoming 5G mobile communications system promises to enable use cases requiring ultra-reliable and low latency communications. Researchers therefore require more detailed information about aspects such as channel coding performance at very low block error rates. The simulations needed to obtain such results are very time consuming and this poses achallenge to studying the problem. This thesis investigates the use of hardware acceleration for performing fast simulations of turbo code performance. Special interest is taken in investigating different methods for generating normally distributed noise based on pseudorandom number generator algorithms executed in DSP:s. A comparison is also done regarding how well different simulator program structures utilize the hardware. Results show that even a simple program for utilizing parallel DSP:s can achieve good usage of hardware accelerators and enable fast simulations. It is also shown that for the studied process the bottleneck is the conversion of hard bits to soft bits with addition of normally distributed noise. It is indicated that methods for noise generation which do not adhere to a true normal distribution can further speed up this process and yet yield simulation quality comparable to methods adhering to a true Gaussian distribution. Overall, it is show that the proposed use of hardware acceleration in combination with the DSP software simulator program can in a reasonable time frame generate results for turbo code performance at block error rates as low as 10−9.