Decision Feedback Equalization (DFE) in a data recovery channel filters the bit decision in the current symbol period in generating the sample at the comparator in the subsequent clock period. The operations of sampling, comparing, filtering the decision bits into a feedback signal, and subtraction of that feedback signal are cascaded, thereby establishing the critical timing path. Thus, this system, though simple, requires its components to have large bandwidths in order to achieve the high-speed response necessary to perform the described feedback function. For the entire system to run at speeds comparable to those of competing technologies (100MHz to 250MHz), the components must have bandwidths greater than 100MHz, and work together to provide a loop bandwidth of at least 100MHz. A 300MHz latching comparator and a 125MHz 6-bit current-DAC were designed in a 5V, 1 um CMOS n-well process for use in a DFE loop. Both blocks are fully differential and achieve an accuracy of 1/2 LSB (10uA) over a differential signal range of 1.28mA. This is true for their operations at speed, in isolated simulation and as contiguous blocks. The DAC power consumption is relatively high at 23mW, due to internal switching circuits which require a static current, but the comparator's power consumption is minimal at 5mW. / Graduation date: 1997

Graduation date: 1994

Thesis (M.A.)--Kutztown University of Pennsylvania, 2000. / Source: Masters Abstracts International, Volume: 45-06, page: 2707. Typescript. Abstract precedes thesis title page as [2] preliminary leaves. Copy 2 in Main Collection. Includes bibliographical references (leaves 108-115).

No description available.

No description available.

This thesis presents a stable technique for distribution of data in Time Interleaved Digital-to-Analog Converters (TIDAC) that allows usage of the entire Nyquist bandwidth. The data distribution uses a Thiran all-pass filter to ensure stability and preserve the phase in the bandwidth of interest. Also, an online technique to compensate for the gain error mismatch in different channels and a skew error calibration technique for open loop configuration is proposed. For the over-all sampling rate of FS, i.e. bandwidth of FS/2 (according to Nyquist), this proposed technique allows calibration of skew error for input signal for most of the Nyquist bandwidth where frequency translation is applied to the input signal to provide calibration in the lower half of the Nyquist band. The simulation results for a 2-channel 14-bit current steering binary weighted TIDAC shows a substantial improvement in SNDR after calibration for input signals up to Nyquist frequency.

No description available.

Thesis (M.S.)--Oregon State University, 2006. / Printout. Includes bibliographical references (leaves 55-58). Also available on the World Wide Web.

Thesis (Ph. D.)--Washington State University, August 2006. / Includes bibliographical references (p. 77-79).

Delta-Sigma Analog-to Digital Converters have recently become important for providing high resolution with monotonicity and reasonable signal-to-distortion ratings without the need for laser trimming techniques. This has come about because of the recent ability to combine both extensive digital computation power, and switched-capacitor analog circuitry on a monolithic chip. Delta-Sigma converters have primarily been used, however, in signal processing applications, notably digital audio, but not for instrumentation. The purpose of this dissertation is to provide a high accuracy, DC-accurate, Delta-Sigma Analog-to-Digital converter in monolithic form. Autocalibration gives endpoint correction, and chopper stabilization minimizes the effect of parameter shifts, drift, and flicker noise. A digital filter, needed for all Delta-Sigma converters, serves as a signal processor to reject out-of-band noise and resonant responses of the external system. A 3-micron, double-poly CMOS process is used. Power requirements are +/- 5 Volts. A six-pole Gaussian IIR digital filter is chosen for good transient response and no overshoot. The filter algorithm and hardware solve the difference equations of a low-pass switched-capacitor prototype filter in digital form. Due to the low bandwidth needed, an area-efficient shift-and-add architecture is used. The area is further reduced with a novel multiplication algorithm, and the logic is reused to perform the calculations required for calibration. The system level device performance is verified in FORTRAN. The analog subcircuits are simulated over process and temperature corners in HSPICE. Measurements show differential and integral linearlity, DC accuracy and noise near the 20-bit level. Power supply rejection, and out-of-band signal attenuation are good, and the step response is monotonic. The circuit is marketed as Crystal Semiconductor CSC5503 and CSC5501 (20 and 16-bit resolutions, respectively).