No description available.

Thesis (M.S.)--University of Texas at Dallas, 2006 / Includes vita. Includes bibliographical references (leaves 97-98)

Thesis (MS)--Montana State University--Bozeman, 2008. / Typescript. Chairperson, Graduate Committee: James P. Becker. Includes bibliographical references (leaves 147-148).

Thesis (M.E.)--University of Canterbury, 2008. / Typescript (photocopy). "June 2008." Includes bibliographical references (p. [89]-92). Also available via the World Wide Web.

No description available.

Conventional CMOS (the current dominant technology for VLSI) implemented with ever smaller transistors is expected to encounter serious problems in the near future with the need for difficult fabrication technologies. The most important problem is heat generation. The desire for device density, power dissipation and performance improvement necessitates new technologies that will provide innovative solutions to integration and computations. Nanotechnology, especially Quantum-dot Cellular Automata (QCA) provides new possibilities for computing owing to its unique properties. Numerous nanoelectronic devices are being investigated and many experimental devices have been developed. Thus, high level circuit design is needed to keep pace with changing physical studies. The circuit design aspects of QCA have not been studied much because of its novelty. Arithmetic units, especially multipliers and dividers play an important role in the design of digital processors and application specific systems. Therefore, designs for parallel multipliers and dividers are presented using this technology. Optimal design of parallel multipliers for Quantum-Dot Cellular Automata is explored in this dissertation. As a main basic element to build multipliers, adders are implemented and compared their performances with previous adders. And two different layout schemes that single layer and multi-layer wire crossings are compared and analyzed. This dissertation proposes three kinds of multipliers. Wallace and Dadda parallel multipliers, quasi-modular multipliers, and array multipliers are designed and simulated with several different operand sizes. Also array multipliers that are well suited in QCA are constructed and formed by a regular lattice of identical functional units so that the structure is conformable to QCA technology without extra wire delay. All these designs are constructed using coplanar layouts and compared with other QCA multipliers. The delay, area and complexity are compared for several different operand sizes. This research also studies divider designs for quantum-dot cellular automata. A digit recurrence restoring binary divider is a conventional design that serves as a baseline. By using controlled full subtractor cell units, a relatively simple and efficient implementation is realized. The Goldschmidt divider using the new architecture (data tag method) to control the various elements of the divider is compared for the performance. / text

This thesis describes the design, implementation and testing of a UHF frequency synthesizer. The synthesizer is designed to provide a sine wave output programmable from 400 MHz to 500 MHz in 0.1 MHz increments. The synthesis technique utilized is Digital Coherent Indirect Synthesis. This technique uses phase locking to provide a range of stable output frequencies all derived from a single crystal reference. Component design and system level analysis are presented in detail.

Integration of more communication standards in one microwave wireless device created a demand on developing compact, low-cost, and robust multi-band microwave components. This dissertation presents three studies for designing miniaturized and multi-band circuits that can be used for multi-band radio frequency (RF) front-ends. These three studies are the design of dual-band and tunable bandpass filters as well as dual- and triple-band equal-split power dividers/combiners. The dual-band filter is based on split ring resonators and double slit complemantary split ring resonators. A dual-band prototype three-stage Chebyshev filter, with a fractional bandwidth of 2% at 0.9 GHz and a fractional bandwidth of 3% at 1.3 GHz with equal-ripple of 0.4 dB at both passbands, is presented. The overall size of the dual-band filter is three times smaller compared to edge-coupled microstrip filters. Good out-of-band signal rejection (< 38 dB) and insertion losses (< 4.9 dB for the lower passband and <2.7 dB for the upper passband) are achieved. The proposed tunable filter is designed from varactor loaded split ring resonators. The size of the tunable filter is reduced by a factor of 3.5 compared to quarter wavelength-based coupled line filters.The power divider is based on composite right- and left-handed transmission lines. Dual-band and triple-band power divider prototypes are designed, fabricated, and tested. The passbands of the triple-band Wilkinson power divider are centered at 0.8 GHz, 1.3 GHz, and 1.85 GHz, and the passbands of the dual-band Wilkinson power divider are centered at 0.7 GHz, 1.5 GHz. The triple-band divider has a length of 0.66 wavelength in the substrate and its size is reduced to 3/4 of right-handed transmission line-based Wilkinson power dividers. The dual-band power divider has wide fractional bandwidths ( 20% at the lower passband and 41% at the upper passband). Excellent input matchings (input return losses < 29 dB), output matchings (output return losses < 23 dB), and output port isolations (< 24 dB) are achieved at all passbands of the power dividers. The proposed filters and power dividers are compact and low-cost, and are promising candidates for the miniaturization and cost-reduction of multi-band microwave wireless system.

In this work, a programmable frequency divider suitable for millimeter wave phase-lock loops is presented. The frequency divider has been implemented in a 90 nm standard CMOS technology. To the extent of maximizing the operative input frequency, the higher frequency digital blocks of the frequency divider have been realized using dynamic precharge-evaluation logic. Moreover, a non-conventional method to implement non-power-of-2 division ratios has been used for the higher frequency divider stages (input stages).

Το αντικείμενο της παρούσας διπλωματικής εργασίας είναι ο σχεδιασμός και η υλοποίηση ενός ταλαντωτή εμβολής, ο οποίος θα μπορεί να χρησιμοποιηθεί και ως διαιρέτης συχνοτήτων. Ο ταλαντωτής και ο διαιρέτης συχνοτήτων, αποτελούν εξέχουσας σημασίας δομικά στοιχεία των RF πομποδεκτών και τοποθετούνται κατά κύριο λόγο μέσα στο βρόχο κλειδώματος φάσης-PLL, ο οποίος επιλέγεται ως συνθέτης συχνοτήτων στα περισσότερα ασύρματα τηλεπικοινωνιακά συστήματα. Αφού μελετήσαμε τη δομή και τις κυριότερες τοπολογίες που χρησιμοποιούνται στη σχεδίαση των ταλαντωτών, προχωρήσαμε στην ανάλυση της εφαρμογή της μεθόδου της εμβολής (injection locking), με σκοπό τη βελτίωση των χαρακτηριστικών της εξόδου τους και ιδιαίτερα τη μείωση του θορύβου φάσης. Επίσης, περιγράφονται τα βασικά χαρακτηριστικά των αναλογικών και των ψηφιακών διαιρετών, ενώ δίνεται ιδιαίτερη έμφαση στην ανάλυση της λειτουργίας των αναλογικών διαιρετών συχνότητας που βασίζονται σε ταλαντωτές εμβολής και είναι ευρύτερα γνωστοί ως injection-locked διαιρέτες συχνότητας (ILFDs). Η επιλογή για περαιτέρω μελέτη και υλοποίηση ενός Colpitts και ενός διαφορικού ταλαντωτή, βασίστηκε στα πλεονεκτήματα που παρουσιάζουν οι συγκεκριμένες τοπολογίες, με αποτέλεσμα την ευρεία χρήση τους σε RF εφαρμογές υψηλών συχνοτήτων. Επίσης οι ταλαντωτές εμβολής που προκύπτουν από τους ταλαντωτές αυτούς, επιδεικνύουν χαμηλή κατανάλωση ισχύος και πολύ καλή συμπεριφοράς ως προς τον θόρυβο φάσης. Ως συχνότητα λειτουργίας των προτεινόμενων κυκλωμάτων, επιλέχθηκε η πολύ σημαντική για τα ασύρματα συστήματα τηλεπικοινωνιών, συχνότητα των 5GHz. Προτείνεται και υλοποιείται λοιπόν ένας Colpitts ταλαντωτής και ο αντίστοιχος ταλαντωτής εμβολής, όπου όπως αποδεικνύεται τόσο από τις εξομοιώσεις όσο και από τα πειραματικά αποτελέσματα, μπορεί να λειτουργεί ως διαιρέτης συχνότητας δια-2 (Divide-by-2 ILFD). Από τα αποτελέσματα που προέκυψαν από τη μέτρηση του υλοποιημένου ταλαντωτή εμβολής, γίνεται ακόμη αντιληπτό ότι ο θόρυβος φάσης είναι εμφανώς βελτιωμένος, όπως αναμενόταν λόγω της εφαρμογής του σήματος εμβολής. Τέλος, σχεδιάστηκε και εξομοιώθηκε ένας διαφορικός ταλαντωτής (differential oscillator), από τον οποίο με κατάλληλη τροποποίηση της τοπολογίας του, προέκυψε ένας injection-locked divide-by-2 διαιρέτης συχνότητας. Το συγκεκριμένο κύκλωμα χρησιμοποιείται ευρέως για τη λειτουργία της διαίρεσης δια-2, εξαιτίας του ότι η τοπολογία του παρέχει ένα φυσικό divide-by-2 injection σημείο. / The subject of the present diplomatic project is the design and implementation of an injection locked oscillator, which might also be used as a frequency divider. The oscillator and the frequency divider, constitute distinguished important structural elements of RF transceivers and are mostly placed into the phase-locked-loop (PLL), which is selected as frequency synthesizer in most wireless telecommunications systems. After we studied the structure and the main topologies used in the design of oscillators, we advanced in the analysis and the application of injection locking method, aiming at the improvement of characteristics of their output and particularly the reduction of phase noise. Also, the basic characteristics of analog and digital dividers are described, while particular emphasis is given in the analysis of operation of analog frequency dividers that is based on injection-locked oscillators, more widely known as injection-locked frequency dividers (ILFDs). The choice for further study and implementation of a Colpitts and differential oscillator, was based on the advantages of the particular topologies, which result in their wide use in high-frequencies RF applications. Also the injection-locked oscillators that result from these oscillators, demonstrate low power consumption and very good behavior as far the phase noise. As operation frequency for the proposed circuits, was selected the very important for the wireless telecommunications systems, frequency of 5GHz. Therefore, it is proposed and implemented a Colpitts oscillator and the corresponding injection-locked oscillator, where as it is proved by the simulations as much as by the experimental results, can function as a divide-by-2 injection-locked frequency divider. From the results that resulted from the measurement of implemented injection-locked oscillator, it becomes clear that the phase noise is obviously improved, as it was expected due to the application of the injection signal. Finally, a differential oscillator was designed and simulated, from which with suitable modification of its topology, resulted a divide-by-2 injection-locked frequency divider. This particular circuit is used widely for the operation of division by-2, because its topology provides a natural divide-by-2 injection point.