In the modern world of technology, highly sophisticated electronic systems pave the way for future's information technology breakthroughs. However, rapid growth on complexity and functions in such systems has also been a harbinger for the power increase. Power management techniques have thus been introduced to mitigate this urgent power crisis. Switching power converters are considered to be the best candidate due to their high efficiency and voltage conversion flexibility. Moreover, switching power converter systems are highly nonlinear, discontinuous in time, and variable. This makes it viable over a wide operating range, under various load and line disturbances. However, only one control scheme cannot optimize the whole system in different scenarios. Hybrid control schemes are thus employed in the power converters to operate jointly and seamlessly for performance optimization during start-up, steady state and dynamic voltage/load transient state.In this dissertation, three switching power converter topologies, along with different hybrid control schemes are studied. First, an integrated switching buck converter with a dual-mode control scheme is proposed. A pulse-train (PT) control, employing a combination of four pulse control patterns, is proposed to achieve optimal regulation performance. Meanwhile, a high-frequency pulse-width modulation (PWM) control is adopted to ensure low output ripples and avoid digital limit cycling. Second, an integrated buck-boost converter with a tri-mode digital control is presented. It employs adaptive step-up/down voltage conversion to enable a wide range of output voltage. This is beneficial to ever-increasing dynamic voltage scaling (DVS) enabled, modern power-efficient VLSI systems. DVS adaptively adjusts the supply voltage and operation frequency according to instantaneous power and performance demand, such that a system is constantly operated at the lowest possible power level without compromising its performance. Third, a digital integrated single-inductor multiple-output (SIMO) converter, tailored for DVS-enabled multicore systems is addressed. With a multi-mode control algorithm, DVS tracking speed and line/load regulation are significantly improved, while the converter still retains low cross regulation.All three integrated CMOS DC-DC converters have been designed and fabricated successfully, demonstrating the techniques proposed in this research. The measurements results illustrate superior line and load regulation performances and dynamic response in all these designs.

In modern digital audio applications, a continuous audio signal stream is sampled at a fixed sampling rate, which is always greater than twice the highest frequency of the input signal, to prevent aliasing. A more energy efficient approach is to dynamically change the sampling rate based on the input signal. In the dynamic sampling rate technique, fewer samples are processed when there is little frequency content in the samples. The perceived quality of the signal is unchanged in this technique. Processing fewer samples involves less computation work; therefore processor speed and voltage can be reduced. This reduction in processor speed and voltage has been shown to reduce power consumption by up to 40% less than if the audio stream had been run at a fixed sampling rate.

Among most severe power system disturbances those degrading power quality are voltage sags and transient interruptions. Even voltage sags lasting only a few tens of milliseconds are enough to bring entire production lines to standstill, causing considerable economic damage as well as endangering the production equipment. Therefore necessary measures have to be taken to protect sensitive loads which are susceptible to these voltage disturbances. Among the solution candidates such as, Uninterruptible Power Supplies, Motor-Generator Sets, etc, Dynamic Voltage Restorer (DVR) which is an effective custom power device has been proposed to mitigate such bus voltage sags on sensitive loads with its excellent dynamic performance. In this study, load side connected shunt converter topology was chosen for the implementation of DVR. The performance DVR was tried to be improved by improving the control strategy used. Super Film located in Gaziantep which is one of the SANKO subsidiary company was chosen to simulate the operation of DVR as actual case of Turkish industry. All the simulations in this study were carried on PSCAD/EMTDC Software.

Η αστάθεια τάσης αποτελεί ένα σημαντικό πρόβλημα για τα συστήματα ηλεκτρικής ενέργειας. Ένα σύστημα εισέρχεται σε κατάσταση αστάθειας τάσης λόγω αύξησης της ζήτησης, μιας ξαφνικής, ευρείας κλίμακας διαταραχής ή αλλαγής στην κατάσταση του, που μπορεί να προκαλέσει μια σταδιακή και ανεξέλεγκτη πτώση τάσης. Παρουσιάζει, λοιπόν, ιδιαίτερο ενδιαφέρον η μεταβατική συμπεριφορά του συστήματος σε σχέση με την ευστάθεια της τάσης. Επίσης, κατά τη λειτουργία ενός Σ.Η.Ε., είναι σημαντικό για το χειριστή να γνωρίζει το μέγιστο επιτρεπτό φορτίο του συστήματος χωρίς να κινδυνεύει από αστάθεια τάσης. Η δυναμική ευστάθεια τάσης μπορεί να διαιρεθεί σε βραχυπρόθεσμη και μακροπρόθεσμη. Στην παρούσα διπλωματική εργασία θα δώσουμε έμφαση στη βραχυπρόθεσμη ευστάθεια τάσης. Για το σκοπό αυτό, αναπτύσσονται δυναμικά μοντέλα που περιγράφουν τη λειτουργία απλών συστημάτων ηλεκτρικής ενέργειας στο περιβάλλον του MATLAB/SIMULINK. Διερευνάται η επίδραση του φορτίου επαγωγικού κινητήρα ενός απλού Σ.Η.Ε., όσον αφορά στη βραχυπρόθεσμη ευστάθεια τάσης, χρησιμοποιώντας τις P-V καμπύλες τόσο του κινητήρα όσο και του δικτύου. Τα αποτελέσματα που προκύπτουν, κατόπιν επαληθεύονται παρατηρώντας τις καταστάσεις του συστήματος στο πεδίο του χρόνου. Με την ανάλυση φαίνεται ότι με την ανάλυση φαίνεται ότι μετά από βραχυκύκλωμα η τάση του συστήματος μειώνεται δραστικά και αυτό μπορεί να προκαλέσει την κατάρρευση του συστήματος όταν αυτό έχει ως φορτίο επαγωγικό κινητήρα. Η κατάρρευση αυτή μπορεί να αποφευχθεί με την όσο το δυνατόν ταχύτερη εκκαθάριση του σφάλματος. Σημαντικός παράγων γι’ αυτό είναι ο καθορισμός του κρίσιμου χρόνου εκκαθάρισης του σφάλματος με σκοπό την αποφυγή της εμφάνισης αστάθειας. Το πρόβλημα αυτό αναλύεται διεξοδικά και ορίζονται με αναλυτικό τρόπο τόσο ο κρίσιμος χρόνος εκκαθάρισης όσο και η κρίσιμη τιμή της ολίσθησης του επαγωγικού κινητήρα. Χρησιμοποιώντας επιπλέον χωρητική αντιστάθμιση αέργου ισχύος αναλύεται ο τρόπος που αυτή βελτιώνει τα περιθώρια ευσταθούς λειτουργίας κατά τη διάρκεια σφαλμάτων. Στη συνέχεια, για τον καθορισμό ενός δείκτη ευστάθειας τάσης σε σχέση με το μέγιστο επιτρεπτό φορτίο σε ένα δίκτυο, περιγράφεται μία διαδικασία καθορισμού ενός τέτοιου δείκτη, η οποία βασίζεται στη σύνθετη τιμή της τάσης όλων των ζυγών ενός συστήματος. Ο προτεινόμενος δείκτης χρησιμοποιείται για την εκτίμηση της μέγιστης φόρτισης του συστήματος. Επιπροσθέτως, καθορίζονται τα πιο «αδύναμα» τμήματα του συστήματος (κρίσιμος ζυγός και κρίσιμη γραμμή) για κατάλληλη άεργο αντιστάθμιση προς αποφυγή κατάρρευσης της τάσης. / Voltage instability has been a great concern for quite a long time in electric power industry. A system enters a state of voltage instability due to increase in demand, a sudden large disturbance or a change in system condition that causes a progressive and uncontrollable decline in voltage. It is therefore interesting to study both the dynamic and static aspects of voltage stability. Dynamic voltage stability can be divided into short-term and long-term based on the dynamics of the components that affect the voltage stability. In this project, we will emphasize on short-term stability. In this study, dynamic models of various power system components are successfully developed in MATLAB/SIMULINK platform. The effect of induction motor load on short-term voltage stability of a simple power system is investigated using the network and motor P-V curves and the results are found and then verified by observing the system states in time domain. Once the reason of voltage instability is identified, a remedial action using fixed capacitive reactive support is suggested to prevent the voltage instability. During a fault, the system voltage reduces drastically and that may cause to stall the induction motors. Stalling of induction motor can be prevented by clearing the fault as quickly as possible. A technique of determining the critical fault clearing time to prevent stalling of induction motor is also presented. In power system operation, it is important for the dispatcher to have knowledge on the maximum permissible loading of the system without reaching voltage instability. In this study, a method of determining the voltage stability index of a system based on the complex voltage of all buses in the system is described. The proposed index is then used in estimating the maximum loading of the system and is based on the information of present and past operating points. In addition, the weakest segments (critical bus and critical line) of the system are also identified for appropriate reactive compensations to avoid voltage collapse. The correctness of the identified critical bus and critical line is then verified by placing shunt/series capacitors at various locations and comparing the corresponding critical load multiplier factors

Η αστάθεια τάσης αποτελεί ένα σημαντικό πρόβλημα για τα συστήματα ηλεκτρικής ενέργειας. Ένα σύστημα εισέρχεται σε κατάσταση αστάθειας τάσης λόγω αύξησης της ζήτησης, μιας ξαφνικής, ευρείας κλίμακας διαταραχής ή αλλαγής στην κατάσταση του, που μπορεί να προκαλέσει μια σταδιακή και ανεξέλεγκτη πτώση τάσης. Παρουσιάζει, λοιπόν, ιδιαίτερο ενδιαφέρον η μεταβατική συμπεριφορά του συστήματος σε σχέση με την ευστάθεια της τάσης. Επίσης, κατά τη λειτουργία ενός Σ.Η.Ε., είναι σημαντικό για το χειριστή να γνωρίζει το μέγιστο επιτρεπτό φορτίο του συστήματος χωρίς να κινδυνεύει από αστάθεια τάσης. Η δυναμική ευστάθεια τάσης μπορεί να διαιρεθεί σε βραχυπρόθεσμη και μακροπρόθεσμη. Στην παρούσα διπλωματική εργασία θα δώσουμε έμφαση στη βραχυπρόθεσμη ευστάθεια τάσης. Για το σκοπό αυτό, αναπτύσσονται δυναμικά μοντέλα που περιγράφουν τη λειτουργία απλών συστημάτων ηλεκτρικής ενέργειας στο περιβάλλον του MATLAB/SIMULINK. Διερευνάται η επίδραση του φορτίου επαγωγικού κινητήρα ενός απλού Σ.Η.Ε., όσον αφορά στη βραχυπρόθεσμη ευστάθεια τάσης, χρησιμοποιώντας τις P-V καμπύλες τόσο του κινητήρα όσο και του δικτύου. Τα αποτελέσματα που προκύπτουν, κατόπιν επαληθεύονται παρατηρώντας τις καταστάσεις του συστήματος στο πεδίο του χρόνου. Με την ανάλυση φαίνεται ότι με την ανάλυση φαίνεται ότι μετά από βραχυκύκλωμα η τάση του συστήματος μειώνεται δραστικά και αυτό μπορεί να προκαλέσει την κατάρρευση του συστήματος όταν αυτό έχει ως φορτίο επαγωγικό κινητήρα. Η κατάρρευση αυτή μπορεί να αποφευχθεί με την όσο το δυνατόν ταχύτερη εκκαθάριση του σφάλματος. Σημαντικός παράγων γι’ αυτό είναι ο καθορισμός του κρίσιμου χρόνου εκκαθάρισης του σφάλματος με σκοπό την αποφυγή της εμφάνισης αστάθειας. Το πρόβλημα αυτό αναλύεται διεξοδικά και ορίζονται με αναλυτικό τρόπο τόσο ο κρίσιμος χρόνος εκκαθάρισης όσο και η κρίσιμη τιμή της ολίσθησης του επαγωγικού κινητήρα. Χρησιμοποιώντας επιπλέον χωρητική αντιστάθμιση αέργου ισχύος αναλύεται ο τρόπος που αυτή βελτιώνει τα περιθώρια ευσταθούς λειτουργίας κατά τη διάρκεια σφαλμάτων. Στη συνέχεια, για τον καθορισμό ενός δείκτη ευστάθειας τάσης σε σχέση με το μέγιστο επιτρεπτό φορτίο σε ένα δίκτυο, περιγράφεται μία διαδικασία καθορισμού ενός τέτοιου δείκτη, η οποία βασίζεται στη σύνθετη τιμή της τάσης όλων των ζυγών ενός συστήματος. Ο προτεινόμενος δείκτης χρησιμοποιείται για την εκτίμηση της μέγιστης φόρτισης του συστήματος. Επιπροσθέτως, καθορίζονται τα πιο «αδύναμα» τμήματα του συστήματος (κρίσιμος ζυγός και κρίσιμη γραμμή) για κατάλληλη άεργο αντιστάθμιση προς αποφυγή κατάρρευσης της τάσης. / Voltage instability has been a great concern for quite a long time in electric power industry. A system enters a state of voltage instability due to increase in demand, a sudden large disturbance or a change in system condition that causes a progressive and uncontrollable decline in voltage. It is therefore interesting to study both the dynamic and static aspects of voltage stability. Dynamic voltage stability can be divided into short-term and long-term based on the dynamics of the components that affect the voltage stability. In this project, we will emphasize on short-term stability. In this study, dynamic models of various power system components are successfully developed in MATLAB/SIMULINK platform. The effect of induction motor load on short-term voltage stability of a simple power system is investigated using the network and motor P-V curves and the results are found and then verified by observing the system states in time domain. Once the reason of voltage instability is identified, a remedial action using fixed capacitive reactive support is suggested to prevent the voltage instability. During a fault, the system voltage reduces drastically and that may cause to stall the induction motors. Stalling of induction motor can be prevented by clearing the fault as quickly as possible. A technique of determining the critical fault clearing time to prevent stalling of induction motor is also presented. In power system operation, it is important for the dispatcher to have knowledge on the maximum permissible loading of the system without reaching voltage instability. In this study, a method of determining the voltage stability index of a system based on the complex voltage of all buses in the system is described. The proposed index is then used in estimating the maximum loading of the system and is based on the information of present and past operating points. In addition, the weakest segments (critical bus and critical line) of the system are also identified for appropriate reactive compensations to avoid voltage collapse. The correctness of the identified critical bus and critical line is then verified by placing shunt/series capacitors at various locations and comparing the corresponding critical load multiplier factors

Made available in DSpace on 2014-06-12T15:49:47Z (GMT). No. of bitstreams: 1 license.txt: 1748 bytes, checksum: 8a4605be74aa9ea9d79846c1fba20a33 (MD5) Previous issue date: 2009 / A grande expansão do mercado de dispositivos digitais tem forçado empresas desenvolvedoras de sistemas embarcados em lidar com diversos desafios para prover sistemas complexos nesse nicho de mercado. Um dos desafios prominentes está relacionado ao consumo de energia, principalmente, devido aos seguintes fatores: (i) mobilidade; (ii) problemas ambientais; e (iii) o custo da energia. Como consequência, consideráveis esforços de pesquisa têm sido dedicados para a criação de técnicas voltadas para aumentar a economia de energia. Na última década, diversas técnicas foram desenvolvidas para reduzir o consumo de energia em sistemas embarcados. Muitos métodos lidam com gerenciamento dinâmico de energia (DPM), como, por exemplo, dynamic voltage scaling (DVS), cooperativamente com sistemas operacionais especializados, a fim de controlar o consumo de energia durante a execução do sistema. Entretanto, apesar da disponibilidade de muitos métodos de redução de consumo de energia, diversas questões estão em aberto, principalmente, no contexto de sistemas de tempo real crítico. Este trabalho propõe um método de síntese de software, o qual leva em consideração relação entre tarefas, overheads, restrições temporais e de energia. O método é composto por diversas atividades, as quais incluem: (i) medição; (ii) especificação; (iii) modelagem formal; (vi) escalonamento; e (v) geração de código. O método também é centrado no formalismo redes de Petri, o qual define uma base para geração precisa de escalas em tempo de projeto, adotando DVS para reduzir o consumo de energia. A partir de uma escala viável, um código customizado é gerado satisfazendo as restrições especificadas, e, dessa forma, garantindo previsibilidade em tempo de execução. Para lidar com a natureza estática das escalas geradas em tempo de projeto, um escalonador simples em tempo de execução é também proposto para melhorar o consumo de energia durante a execução do sistema. Diversos experimentos foram conduzidos, os quais demonstram a viabilidade da abordagem proposta para satisfazer restrições críticas de tempo e energia. Adicionalmente, um conjunto integrado de ferramentas foram desenvolvidas para automatizar algumas atividades do método de síntese de software proposto

Emergent systems in high-performance computing (HPC) expect maximal efficiency to achieve the goal of power budget under 20-40 megawatts for 1 exaflop set by the Department of Energy. To optimize efficiency, emergent systems provide multiple power-performance control techniques to throttle different system components and scale of concurrency. In this dissertation, we focus on three throttling techniques: CPU dynamic voltage and frequency scaling (DVFS), dynamic memory throttling (DMT), and dynamic concurrency throttling (DCT). We first conduct an empirical analysis of the performance and energy trade-offs of different architectures under the throttling techniques. We show the impact on performance and energy consumption on Intel x86 systems with accelerators of Intel Xeon Phi and a Nvidia general-purpose graphics processing unit (GPGPU). We show the trade-offs and potentials for improving efficiency. Furthermore, we propose a parallel performance model for coordinating DVFS, DMT, and DCT simultaneously. We present a multivariate linear regression-based approach to approximate the impact of DVFS, DMT, and DCT on performance for performance prediction. Validation using 19 HPC applications/kernels on two architectures (i.e., Intel x86 and IBM BG/Q) shows up to 7% and 17% prediction error correspondingly. Thereafter, we develop the metrics for capturing the performance impact of DVFS, DMT, and DCT. We apply the artificial neural network model to approximate the nonlinear effects on performance impact and present a runtime control strategy accordingly for power capping. Our validation using 37 HPC applications/kernels shows up to a 20% performance improvement under a given power budget compared with the Intel RAPL-based method. / Ph. D. / System efficiency on high-performance computing (HPC) systems is the key to achieving the goal of power budget for exascale supercomputers. Techniques for adjusting the performance of different system components can help accomplish this goal by dynamically controlling system performance according to application behaviors. In this dissertation, we focus on three techniques: adjusting CPU performance, memory performance, and the number of threads for running parallel applications. First, we profile the performance and energy consumption of different HPC applications on both Intel systems with accelerators and IBM BG/Q systems. We explore the trade-offs of performance and energy under these techniques and provide optimization insights. Furthermore, we propose a parallel performance model that can accurately capture the impact of these techniques on performance in terms of job completion time. We present an approximation approach for performance prediction. The approximation has up to 7% and 17% prediction error on Intel x86 and IBM BG/Q systems respectively under 19 HPC applications. Thereafter, we apply the performance model in a runtime system design for improving performance under a given power budget. Our runtime strategy achieves up to 20% performance improvement to the baseline method.

No description available.

This dissertation studies the problem of increasing battery life-time and reducing CPU heat dissipation without degrading system performance in commodity-OS-based general-purpose (GP) mobile computers using the dynamic voltage scaling (DVS) function of modern CPUs. The dissertation especially focuses on the impact of task scheduling on the effectiveness of DVS in achieving this goal. The task scheduling mechanism used in most contemporary general-purpose operating systems (GPOS) prioritizes tasks based only on their CPU occupancies irrespective of their deadlines. In currently available autonomous DVS schemes for GP mobile systems, the impact of this GPOS task scheduling is ignored and a DVS scheme merely predicts and enforces the lowest CPU speed that can meet tasks' deadlines without meddling with task scheduling. This research, however, shows that it is impossible to take full advantage of DVS in balancing energy/power and performance in the current DVS paradigm due to the mismatch between the urgency (i.e., having a nearer deadline) and priority of tasks under the GPOS task scheduling. This research also shows that, consequently, a new DVS paradigm is necessary, where a "DVS-friendly" task scheduling assigns higher priorities to more urgent tasks. The dissertation begins by showing how the mismatch between the urgency and priority of tasks limits the effectiveness of DVS and why conventional real-time (RT) task scheduling, which is intrinsically DVS-friendly cannot be used in GP systems. Then, the dissertation describes the requirements for "DVS-friendly GP" task scheduling as follows. Unlike the existing GPOS task scheduling, it should prioritize tasks by their deadline. But, at the same time, it must be able to do so without a priori knowledge of the deadlines and be able to handle the various tasks running in today's GP systems, unlike conventional RT task scheduling. The various tasks include sporadic tasks such as user-interactive tasks and tasks having dependencies on each other such as a family of threads and user-interface server/clients tasks. Therefore, the first major result of this research is to propose a new DVS paradigm for commodity-OS-based GP mobile systems in which DVS is performed under a DVS-friendly GP task scheduling that meets these requirements. The dissertation then proposes GPSched, a DVS-friendly GP task scheduling mechanism for commodity-Linux-based GP mobile systems, as the second major result. GPSched autonomously prioritizes tasks by their deadlines using the type of services that each task is involved with as the indicator of the deadline. At the same time, GPSched properly handles a family of threads and user-interface server/clients tasks by distinguishing and scheduling them as a group, and user-interactive tasks by incorporating a feature of current GPOS task scheduling — raising the priority of a task that is idle most of the time — which is desirable to quickly respond to user input events in its prioritization mechanism. The final major result is GPScheDVS, the integration of GPSched and a task-based DVS scheme customized for GPSched called GPSDVS. GPScheDVS provides two alternative modes: (1) the system-energy-centric (SE) mode aiming at a longer battery life-time by reducing system energy consumption and (2) the CPU-power-centric (CP) mode focusing on limiting CPU heat dissipation by reducing CPU power consumption. Experiments conducted under a set of real-life usage scenarios on a laptop show that the best, worst, and average reductions of system energy consumption by the SE mode GPScheDVS were 24%, -1%, and 17%, respectively, over the no-DVS case and 11%, -1%, and 5%, respectively, over the state-of-the-art task-based DVS scheme in the current DVS paradigm. The experiments also show that the best, worst, and average reductions of CPU energy consumption by the SE mode GPScheDVS were 69%, 0%, and 43% over the no-DVS case and 26%, -1%, and 13% over the state-of-the-art task-based DVS scheme in the current DVS paradigm. Considering that no power management was performed on non-CPU components for the experiments, these results imply that the system energy savings achievable by GPScheDVS will be increased if the non-CPU components' power is properly managed. On the other hand, the best, worst, and average reductions of average CPU power by the CP mode GPScheDVS were 69%, 49%, and 60% over the no-DVS case and 63%, 0%, and 30% over the existing task-based DVS scheme. Furthermore, oscilloscope measurements show that the best, worst, and average reduction of peak system power by the CP mode GPScheDVS were 29%, 10%, and 23% over the no-DVS case and 28%, 6%, and 22% over the existing task-based DVS scheme signifying that GPScheDVS is effective also in restraining the peak CPU power. On the top of these advantages in energy and power, the experimental results show that GPScheDVS even improves system performance in either mode due to its deadline-based task scheduling property. For example, the deadline meet ratio on continuous videos by GPScheDVS was at least 91.2%, whereas the ratios by the no-DVS case and the existing task-based DVS scheme were down to 71.3% and 71.0%, respectively. / Ph. D.

Current Intel processors implement a variety of power saving features like frequency scaling and idle states. These mechanisms limit the power draw and thereby decrease the thermal dissipation of the processors. However, they also have an impact on the achievable performance. The various mechanisms significantly differ regarding the amount of power savings, the latency of mode changes, and the associated overhead. In this paper, we describe and closely examine the so-called software controlled clock modulation mechanism for different processor generations. We present results that imply that the available documentation is not always correct and describe when this feature can be used to improve energy efficiency. We additionally compare it against the more popular feature of dynamic voltage and frequency scaling and develop a model to decide which feature should be used to optimize inter-process synchronizations on Intel Haswell-EP processors.