Dynamic Voltage Scaling (DVS) and Adaptive body bias (ABB) techniques respectively try to reduce the dynamic and static power components of an integrated circuit. Ideally, the two techniques can be combined to find the optimal operating voltages (VDD and VBB) to minimize power consumption. A combination of the DVS and ABB may warrant the circuit to operate at voltages (supply and body bias) different from the values specified by the two methods working independently. Also, this VDD and VBB values for minimal power consumption varies with the workload of the circuit. The workload can be used as an index to select the optimal VDD/VBB values to minimize the total power consumption. This paper examines the optimal voltages for minimal power operation for typical data path circuits like adders and multiply-accumulate (MAC) units across various process, voltage, and temperature conditions and under different workloads. In addition, a workload based look up table to minimize the power consumption is also proposed. Simulation results for an adder and a multiply-accumulate circuit block indicate a power saving of 12-30% over standard DVS scheme.

Emerging low power, embedded, wireless sensor devices are useful for wide range of applications, yet have very limited processing storage and especially energy resources. Sensor networks have a wide variety of applications in medical monitoring, environmental sensing and military surveillance. Due to the large number of sensor nodes that may be deployed and the required long system lifetimes, replacing the battery is not an option. Sensor systems must utilize the minimal possible energy while operating over a wide range of operating scenarios. The most of the efforts in the energy management in sensor networks have concentrated on minimizing energy consumption in the communication subsystem. Some researchers have also dealt with the issue of minimizing the energy in computing subsystem of a sensor network node. Some proposals using energy aware software have also been made. Relatively little work has been done on compiler controlled energy management in sensor networks. In this thesis, we present our investigations on how compiler techniques can be used to minimize CPU energy consumption in sensor network nodes. One effectively used energy management technique in general purpose processors, is dynamic voltage scaling. In this thesis we implement and evaluate a compiler assisted DVS algorithm and show its usefulness for a small sensor node processor. We were able to achieve an energy saving of 29% with a little performance slowdown. Scratchpad memories have been widely used for improving performance. In this thesis we show that if the scratchpad size for the system is chosen carefully, then large energy savings can be achieved by using a compiler assisted scratchpad allocation policy. With a small size of 512 byte scratchpad memory we were able to achieve 50% of energy savings. We also studied the behavior of dynamic voltage scaling in presence of scratchpad memory. Our results show that in presence of scratchpad memory less opportunities are found for applying dynamic voltage scaling techniques. The sensor network community lacks a comprehensive benchmark suite, for our study we also implemented a set of applications, representative of computational workload on sensor network nodes. The techniques studied in this thesis can easily be integrated with existing energy management techniques in sensor networks, yielding in additional energy savings.

Η παρούσα διπλωματική εργασία έχει ως αντικείμενο τη διερεύνηση της λειτουργίας και το σχεδιασμό συστήματος ελέγχου του δυναμικού αποκαταστάτη τάσης (DVR - Dynamic Voltage Restorer, όπως αναφέρεται στη διεθνή βιβλιογραφία) που χρησιμοποιείται στα δίκτυα διανομής. Η συγκεκριμένη συσκευή ανήκει στην κατηγορία των FACTS (Flexible ac Transmission Systems), παρέχει εν σειρά αντιστάθμιση, και ο σκοπός λειτουργίας της είναι η βελτίωση της ποιότητας της παρεχόμενης ισχύος και η αύξηση της αξιοπιστίας του συστήματος. Εξειδικεύεται στις βυθίσεις τάσεως. Πιο συγκεκριμένα, ο δυναμικός αποκαταστάτης τάσης έχει στόχο, όπως μαρτυρά και το όνομά του, να διατηρεί την τάση ενός φορτίου κατά το δυνατόν σταθερή στην τιμή που αυτή είχε πριν συμβεί η όποια βύθιση. Έτσι, θα καταβληθεί προσπάθεια προκειμένου να προσομοιωθεί η λειτουργία μιας τέτοιας συσκευής σε ένα απλό δίκτυο με τη βοήθεια του λογισμικού PSCAD. Θα κατασκευαστεί ο DVR καθώς και το σύστημα ελέγχου του κι αφού συνδεθεί σε ένα φορτίο, θα δημιουργήσουμε διάφορα είδη σφαλμάτων και θα μελετήσουμε την απόκρισή του και την ικανότητά του να αποκαθιστά την τάση. / This diploma thesis refers to Dynamic Voltage Restorer (DVR), a series compensator used in transmission systems. It is a device that belongs to FACTS and its main function is the mitigation of volatge sags and swells.

Nowadays, national and international electric utilities and end users are becoming more and more concerned about the quality of the electrical power. Such concerns are related with the occurrence of electric disturbances capable to effect the operation and the life expectance of equipments and devices, as well as affecting and interrupting varied industrial processes. Of the above mentioned phenomena, short-duration voltage variations deserve special attention once they are the disturbances that cause the largest damages to the consumers. As a consequence of that, there are several devices available that minimize the effects of such disturbances on the equipments. Among those devices, the Dynamic Voltage Restorer (DVR) represents a modern proposal for the solution of the problems caused by voltage sags and swells. In this work, three different system topologies for DVRs are analysed throughout computer implementations. Comparisons are made between these topologies, with focus on both the general performance and on the electrical power quality of the entire system. / As preocupações com os diversos assuntos relacionados à Qualidade da Energia Elétrica têm sido cada vez mais comuns às empresas de energia e aos consumidores em geral, e vêm assumindo importância destacada nos cenários nacional e internacional. Tais preocupações são voltadas para a ocorrência de distúrbios elétricos capazes de comprometer o desempenho e a vida útil de equipamentos e dispositivos, além de afetar ou interromper variados processos industriais. Desses distúrbios, as VTCDs (Variações de Tensão de Curta Duração) são consideradas as que mais causam prejuízos aos consumidores. Com isso, já existe na literatura técnica uma série de metodologias de prevenção e variados dispositivos de atenuação dos efeitos das VTCDs. Destes dispositivos, destaca-se o Restaurador Dinâmico de Tensão (DVR Dynamic Voltage Restorer) que é um compensador estático série avançado aplicado à distribuição de energia elétrica e que representa hoje o que há de mais moderno em termos de mitigação de afundamentos e elevações de tensão. O presente trabalho visa contribuir para o estudo do desempenho de algumas topologias de DVR, comparando a atuação de três opções de configuração através de simulações computacionais em plataforma SABER. A análise comparativa do desempenho das topologias não considera apenas a eficiência na compensação dos distúrbios elétricos, mas também os efeitos que causam na qualidade da tensão do sistema elétrico, sejam por injeção de harmônicos ou por oscilações transitórias. / Mestre em Ciências

No description available.

This term project deals with the problem of scheduling real-time tasks in overload conditions and techniques for lowering power consumption. Each of these parts features mechanisms and reasons for their using. There are also described specific algorithms, that are implemented, in operating system uC/OS-II, and compared in next phase of master's thesis.

This thesis describes the flexible voltage control of a multi-level-voltage-reinjection voltage source converter. The main purposes are to achieve reactive power generation flexibility when applied for HVdc transmission systems, reduce dynamic voltage balancing for direct series connected switches and an improvement of high power converter efficiency and reliability. Waveform shapes and the impact on ac harmonics caused by the modulation process are studied in detail. A configuration is proposed embracing concepts of multi level, soft-switching and harmonic cancellation. For the configuration, the firing sequence, waveform analysis, steady-state and dynamic performances and close-loop control strategies are presented. In order not to severely compromise the original advantages of the converter, the modulated waveforms are proposed based on the restrictions imposed mathematically by the harmonic cancellation concept and practically by the synthesis circuit complexity and high switching losses. The harmonic impact on the ac power system prompted by the modulation process is studied from idealistic and practical aspects. The circuit topology being proposed in this thesis is developed from a 12-pulse bridge and a converter used classically for inverting power from separated dc sources. Switching functions are deduced and current paths through the converter are analysed. Safe and steady-state operating regions of the converter are studied in phasor diagrams to facilitate the design of simple controllers for active power transfer and reactive power generations. An investigation into the application of this topology to the back-to-back VSC HVdc interconnection is preformed via EMTDC simulations.

In the modern generation, Electric Power has become one of the fundamental needs for humans to survive. This is due to the dependence of continuous availability of power. However, for electric power to be available to the society, it has to pass through a number of complex stages. Through each stage power quality problems are experienced on the grid. Under-voltages and over-voltages are the most common electric problems experienced on the grid, causing industries and business firms losses of Billions of dollars each year. Researchers from different regions are attracted by an idea that will overcome all the electrical issues experienced in the traditional grid using Artificial Intelligence (AI). The idea is said to provide electric power that is sustainable, economical, reliable and efficient to the society based on Evolutionary Algorithms (EAs). The idea is Smart Grid. The research focused on Power Quality Optimization in Smart Grid based on improved Differential Evolution (DE), with the objective functions to minimize voltage swells, counterbalance voltage sags and eliminate voltage surges or spikes, while maximizing the power quality. During Differential Evolution improvement research, elimination of stagnation, better and fast convergence speed were achieved based on modification of DE’s mutation schemes and parameter control selection. DE/Modi/2 and DE/Modi/3 modified mutation schemes proved to be the excellent improvement for DE algorithm by achieving excellent optimization results with regards to convergence speed and elimination of stagnation during simulations. The improved DE was used to optimize Power Quality in smart grid in combination with the reconfigured and modified Dynamic Voltage Restorer (DVR). Excellent convergence results of voltage swells and voltage sags minimization were achieved based on application of multi-objective parallel operation strategy during simulations. MATLAB was used to model the proposed solution and experimental simulations. / Electrical and Mining Engineering / M. Tech. (Electrical Engineering)

Multi functional health monitoring wearable devices are quite prominent these days. Usually these devices are battery-operated and consequently are limited by their battery life (from few hours to a few weeks depending on the application). Of late, it was realized that these devices, which are currently being operated at fixed voltage and frequency, are capable of operating at multiple voltages and frequencies. By switching these voltages and frequencies to lower values based upon power requirements, these devices can achieve tremendous benefits in the form of energy savings. Dynamic Voltage and Frequency Scaling (DVFS) techniques have proven to be handy in this situation for an efficient trade-off between energy and timely behavior. Within imec, wearable devices make use of the indigenously developed MUSEIC v2 (Multi Sensor Integrated circuit version 2.0). This system is optimized for efficient and accurate collection, processing, and transfer of data from multiple (health) sensors. MUSEIC v2 has limited means in controlling the voltage and frequency dynamically. In this thesis we explore how traditional DVFS techniques can be applied to the MUSEIC v2. Experiments were conducted to find out the optimum power modes to efficiently operate and also to scale up-down the supply voltage and frequency. Considering the overhead caused when switching voltage and frequency, transition analysis was also done. Real-time and non real-time benchmarks were implemented based on these techniques and their performance results were obtained and analyzed. In this process, several state of the art scheduling algorithms and scaling techniques were reviewed in identifying a suitable technique. Using our proposed scaling technique implementation, we have achieved 86.95% power reduction in average, in contrast to the conventional way of the MUSEIC v2 chip’s processor operating at a fixed voltage and frequency. Techniques that include light sleep and deep sleep mode were also studied and implemented, which tested the system’s capability in accommodating Dynamic Power Management (DPM) techniques that can achieve greater benefits. A novel approach for implementing the deep sleep mechanism was also proposed and found that it can obtain up to 71.54% power savings, when compared to a traditional way of executing deep sleep mode. / Nuförtiden så har multifunktionella bärbara hälsoenheter fått en betydande roll. Dessa enheter drivs vanligtvis av batterier och är därför begränsade av batteritiden (från ett par timmar till ett par veckor beroende på tillämpningen). På senaste tiden har det framkommit att dessa enheter som används vid en fast spänning och frekvens kan användas vid flera spänningar och frekvenser. Genom att byta till lägre spänning och frekvens på grund av effektbehov så kan enheterna få enorma fördelar när det kommer till energibesparing. Dynamisk skalning av spänning och frekvens-tekniker (såkallad Dynamic Voltage and Frequency Scaling, DVFS) har visat sig vara användbara i detta sammanhang för en effektiv avvägning mellan energi och beteende. Hos Imec så använder sig bärbara enheter av den internt utvecklade MUSEIC v2 (Multi Sensor Integrated circuit version 2.0). Systemet är optimerat för effektiv och korrekt insamling, bearbetning och överföring av data från flera (hälso) sensorer. MUSEIC v2 har begränsad möjlighet att styra spänningen och frekvensen dynamiskt. I detta examensarbete undersöker vi hur traditionella DVFS-tekniker kan appliceras på MUSEIC v2. Experiment utfördes för att ta reda på de optimala effektlägena och för att effektivt kunna styra och även skala upp matningsspänningen och frekvensen. Eftersom att ”overhead” skapades vid växling av spänning och frekvens gjordes också en övergångsanalys. Realtidsoch icke-realtidskalkyler genomfördes baserat på dessa tekniker och resultaten sammanställdes och analyserades. I denna process granskades flera toppmoderna schemaläggningsalgoritmer och skalningstekniker för att hitta en lämplig teknik. Genom att använda vår föreslagna skalningsteknikimplementering har vi uppnått 86,95% effektreduktion i jämförelse med det konventionella sättet att MUSEIC v2-chipets processor arbetar med en fast spänning och frekvens. Tekniker som inkluderar lätt sömn och djupt sömnläge studerades och implementerades, vilket testade systemets förmåga att tillgodose DPM-tekniker (Dynamic Power Management) som kan uppnå ännu större fördelar. En ny metod för att genomföra den djupa sömnmekanismen föreslogs också och enligt erhållna resultat så kan den ge upp till 71,54% lägre energiförbrukning jämfört med det traditionella sättet att implementera djupt sömnläge.