This dissertation proves the feasibility of accurate runtime prediction of processor performance under frequency scaling. The performance predictors developed in this dissertation allow processors capable of dynamic voltage and frequency scaling (DVFS) to improve their performance or energy efficiency by dynamically adapting chip or core voltages and frequencies to workload characteristics. The dissertation considers three processor configurations: the uniprocessor capable of chip-level DVFS, the private cache chip multiprocessor capable of per-core DVFS, and the shared cache chip multiprocessor capable of per-core DVFS. Depending on processor configuration, the presented performance predictors help the processor realize 72–85% of average oracle performance or energy efficiency gains. / text

O restaurador dinâmico de tensão (DVR) é uma solução baseada em eletrônica de potência para minimizar os problemas causados por afundamentos e elevações de tensão em equipamentos ou cargas sensíveis a esses tipos de distúrbios. Basicamente a operação do DVR consiste em injetar na rede tensões de correção com a finalidade de anular o afundamento ou a elevação na tensão aplicada à carga. Tipicamente, a estrutura do controlador utilizado em um DVR é composta por uma malha interna de corrente e uma malha externa de tensão. Usualmente um controlador do tipo proporcional ou proporcional integral é utilizado na malha interna de corrente e um controlador ressonante é utilizado na malha externa de tensão. O presente trabalho apresenta um projeto de controlador robusto para rastreamento da tensão injetada pelo DVR que garante estabilidade robusta do sistema com respeito à variação dos parâmetros da carga. Além disso, o controlador proposto garante valores pré-definidos para o erro de rastreamento e para a rejeição do distúrbio causado por correntes de carga distorcidas na tensão injetada pelo DVR. A síntese do controlador robusto de tensão é feita com base no método de projeto H? pela formulação da sensibilidade mista. Todas as especificações de desempenho e robustez são impostas por meio de restrições nos diagramas de resposta em frequência do sistema em malha fechada (funções sensibilidade e sensibilidade complementar). O desempenho do controlador proposto é verificado e a metodologia de projeto é validada por simulações e experimentos realizados em um DVR de baixa potência. / The Dynamic Voltage Restorer (DVR) is a power electronics based solution for mitigation of voltage sags and swells effects on sensitive loads, which basically injects voltages in series with the grid. Typically the controller structure for a DVR is composed by an inner current loop and an outer voltage loop. Usually proportional or a proportional-integral controller is used for the current loop and a resonant controller is used for the voltage loop. This paper presents the design of a robust controller for the voltage tracking loop of a DVR that guaranties the robust stability against load parameters variation. Moreover, the proposed controller assures the tracking of a sinusoidal voltage waveform, as well the rejection of the non linear load current influence, both with a pre specified error. The voltage controller design is based on H? mix-sensitivity parameter specification approach. All the performance and robustness requirements are specified and analyzed based on the frequency response plot of closed loop transfer function (sensitivity and complementary sensitivity functions). The proposed controller performance is validated by simulation and by experiments carried out on a low scale DVR prototype.

O restaurador dinâmico de tensão (DVR) é uma solução baseada em eletrônica de potência para minimizar os problemas causados por afundamentos e elevações de tensão em equipamentos ou cargas sensíveis a esses tipos de distúrbios. Basicamente a operação do DVR consiste em injetar na rede tensões de correção com a finalidade de anular o afundamento ou a elevação na tensão aplicada à carga. Tipicamente, a estrutura do controlador utilizado em um DVR é composta por uma malha interna de corrente e uma malha externa de tensão. Usualmente um controlador do tipo proporcional ou proporcional integral é utilizado na malha interna de corrente e um controlador ressonante é utilizado na malha externa de tensão. O presente trabalho apresenta um projeto de controlador robusto para rastreamento da tensão injetada pelo DVR que garante estabilidade robusta do sistema com respeito à variação dos parâmetros da carga. Além disso, o controlador proposto garante valores pré-definidos para o erro de rastreamento e para a rejeição do distúrbio causado por correntes de carga distorcidas na tensão injetada pelo DVR. A síntese do controlador robusto de tensão é feita com base no método de projeto H? pela formulação da sensibilidade mista. Todas as especificações de desempenho e robustez são impostas por meio de restrições nos diagramas de resposta em frequência do sistema em malha fechada (funções sensibilidade e sensibilidade complementar). O desempenho do controlador proposto é verificado e a metodologia de projeto é validada por simulações e experimentos realizados em um DVR de baixa potência. / The Dynamic Voltage Restorer (DVR) is a power electronics based solution for mitigation of voltage sags and swells effects on sensitive loads, which basically injects voltages in series with the grid. Typically the controller structure for a DVR is composed by an inner current loop and an outer voltage loop. Usually proportional or a proportional-integral controller is used for the current loop and a resonant controller is used for the voltage loop. This paper presents the design of a robust controller for the voltage tracking loop of a DVR that guaranties the robust stability against load parameters variation. Moreover, the proposed controller assures the tracking of a sinusoidal voltage waveform, as well the rejection of the non linear load current influence, both with a pre specified error. The voltage controller design is based on H? mix-sensitivity parameter specification approach. All the performance and robustness requirements are specified and analyzed based on the frequency response plot of closed loop transfer function (sensitivity and complementary sensitivity functions). The proposed controller performance is validated by simulation and by experiments carried out on a low scale DVR prototype.

Les performances des algorithmes d'ordonnancement ont un impact direct sur les performances du système complet. Les algorithmes d'ordonnancement temps réel possèdent des bornes théoriques d'ordonnançabilité optimales mais cette optimalité est souvent atteinte au prix d'un nombre élevé d'événements d'ordonnancement à considérer (préemptions et migrations de tâches) et d'une complexité algorithmique importante. Notre opinion est qu'en exploitant plus efficacement les paramètres des tâches il est possible de rendre ces algorithmes plus efficaces et à coût maitrisé, et ce dans le but d'améliorer la Qualité de Service (QoS) des applications. Nous proposons dans un premier temps des algorithmes d'ordonnancement monoprocesseur qui augmentent la qualité de service d'applications hybrides c'est-à-dire qu'en situation de surcharge, les tâches à contraintes souples ont leur exécution maximisée et les échéances des tâches à contraintes strictes sont garanties. Le coût d'ordonnancement de ces algorithmes est aussi réduit (nombre de préemptions) par une meilleure exploitation des paramètres implicites et explicites des tâches. Cette réduction est bénéfique non seulement pour les performances du système mais elle agit aussi positivement sur la consommation d'énergie. Aussi nous proposons une technique associée à celle de DVFS (dynamic voltage and frequency scaling) afin de minimiser le nombre de changements de points de fonctionnement du fait qu'un changement de fréquence implique un temps d'inactivité du processeur et une consommation d'énergie. Les algorithmes d'ordonnancement multiprocesseur basés sur le modèle d'ordonnancement fluide (notion d'équité) atteignent des bornes d'ordonnançabilité optimales. Cependant cette équité n'est garantie qu'au prix d'hypothèses irréalistes en pratique du fait des nombres très élevés de préemptions et de migrations de tâches qu'ils induisent. Dans cette thèse un algorithme est proposé (ASEDZL) qui n'est pas basé sur le modèle d'ordonnancement fluide. Il permet non seulement de réduire les préemptions et les migrations de tâches mais aussi de relâcher les hypothèses imposées par ce modèle d'ordonnancement. Enfin, nous proposons d'utiliser ASEDZL dans une approche d'ordonnancement hiérarchique ce qui permet d'obtenir de meilleurs résultats que les techniques classiques.

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As time goes by rapid development of 3D graphics technique and 3C portable product output, 3D graphics have been widely applied to handheld devices, such as notebooks, PDAs, and smart cellular phones. Generally, to process 3D graphics applications in mobile devices, processor needs strong capability of handling large computational-intensive workloads. Complex computation consumes a great quantity of electric power. But the lifetime of handheld device battery is limited. Therefore, the cost, to satisfy this demand, will be shortening the supply time of device battery. Moreover, Moore¡¦ law said that the number of transistors in a chip is double in every eighteen months. But these days the advance in manufacturing batteries still cannot get up with the advance in developing processors. In addition, the improvement of chip size has led to more small, supply voltage of kernel processor in portable device. Considering system efficiency and battery lifetime simultaneously increase the difficulty of designing power management scheme. So, how to manage power effectively has become one of the important key for designing handheld products. For 3D graphics system, dynamic voltage and frequency scaling (DVFS) is one of good solutions to implement power management policy. DVFS needs an efficient online prediction method to predict the workload of frames and then appropriately adjust voltage and frequency for saving energy consumption. Consequently, a lot of related papers have proposed different prediction policy to predict the executing workload of 3D graphics system. For instance, the existing prediction policies include signature-based[1], history-based[3] and proportion-integral-derivative (PID)[14] methods, but most of designers put power management in software, i.e. processors. This solution not only slows power management to get the information about executing time of graphic processing unit (GPU), but also increases the operating overhead of CPU in handheld system. In this paper, we propose a power management workload prediction scheme with a framework of using proportion-integral (PI) controller to be a master controller and fuzzy controller to be a slave controller, and then implement it into hardware circuit. Taking advantage of fuzzy conception in fuzzy controller is to adjust the proportional parameter in PI controller, the shortage of traditional PI controller that demands on complicated try-and-error method to look for a good proportional and integral parameters can be avoided so that the adaption and forecasting accuracy can be improved. Besides, Uniform Window-size Predictor 1 (UW1) is also implemented as an assistant manner. Using UW1 predictor appropriately can improve the prediction trend to catch up with the trend of real workload. Experimental results show that our predictor improves prediction accuracy about 3.8% on average and saves about 0.02% more energy compared with PI predictor[18]. Circuit area and power consumption only increases 6.8% percent and 1.4% compared with PI predictor. Besides, we also apply our predictor to the 3D first person game, Quake II, in the market. The result shows that our predictor is indeed an effective prediction policy. The adaption can put up with the intense workload variation of real game and adjust voltage and frequency precisely to decrease power consumption and meet the purpose of energy saving.

In modern life, 3D graphics system is widely applied to portable product like Notebook, PDA and smart phone. Unlike desktop system, the capacity of batteries of these embedded systems is finite. Furthermore, rapid improvement of IC process leads to quick growth in the transistor count of a chip. According to above-mentioned reason and the complex computation of 3D graphics system, the power consumption will be very large. To efficiently lengthen the lifetime of battery, power management is an indispensable technique. Dynamic voltage and frequency scaling (DVFS) is one of the popular power management policy. In the scheme of DVFS, an accurate workload predictor is needed to predict the workload of every frame. According to these predictions a specific voltage and frequency level is applied to each frame of the 3D graphics system. The number of the voltage/frequency levels and the voltage/frequency of each level are fixed, the voltage/frequency table is decided according to the application of power management. Whenever the workload predictor completes the workload prediction of next frame, the voltage/frequency level of next frame will be found by looking up the voltage/frequency table. In this thesis, we propose a power management scheme with a framework composed of mainly Kalman filter and an auxiliary fuzzy controller to predict the workload of next frame. This scheme amends the shortcomings of traditional Kalman filter that needs to know the system features beforehand. And we propose a brand new concept named ¡¨delayed display¡¨ to massively reduce the miss rate of prediction without changing the framework of predictor.

Circuit designers perform optimization procedures targeting speed and power during the design of a circuit. Gate sizing can be applied to optimize for speed, while Dual-VT and Dynamic Voltage Scaling (DVS) can be applied to optimize for leakage and dynamic power, respectively. Both gate sizing and Dual-VT are design-time techniques, which are applied to the circuit at a fixed voltage. On the other hand, DVS is a run-time technique and implies that the circuit will be operating at a different voltage than that used during the optimization phase at design-time. After some analysis, the risk of non-critical paths becoming critical paths at run-time is detected under these circumstances. The following questions arise: 1) should we take DVS into account during the optimization phase? 2) Does DVS impose any restrictions while performing design-time circuit optimizations?. This thesis is a case study of applying DVS to a circuit that has been optimized for speed and power, and aims at answering the previous two questions. We used a 45-nm CMOS design kit and flow. Synthesis, placement and routing, and timing analysis were applied to the benchmark circuit ISCAS?85 c432. Logical Effort and Dual-VT algorithms were implemented and applied to the circuit to optimize for speed and leakage power, respectively. Optimizations were run for the circuit operating at different voltages. Finally, the impact of DVS on circuit optimization was studied based on HSPICE simulations sweeping the supply voltage for each optimization. The results showed that DVS had no impact on gate sizing optimizations, but it did on Dual-VT optimizations. It is shown that we should not optimize at an arbitrary voltage. Moreover, simulations showed that Dual-VT optimizations should be performed at the lowest voltage that DVS is intended to operate, otherwise non-critical paths will become critical paths at run-time.

This thesis presents the application of a series interconnection module for small distributed generation (DG) or renewable energy systems integration in the distribution network. The concept used one set of voltage source converter (VSC) with battery energy storage system to control the injected voltage magnitude and phase angle for power injection and voltage sag mitigation applications. Through an energy storage device and the VSC, the module allows storage of surplus energy during off peak period and release for use during daytime peak load period, therefore, exhibits a load leveling characteristic. Due to its series connection characteristic, it is convenient in preventing islanding operation and suitable for voltage sag mitigation. The concept is suitable for locations where the voltage phase shift is not a problem. Due to the use of only one set of VSC, it is economic for customer site distributed energy resource applications.

In the past few years, due to the rapid advance in technology and the aid of 3D graphics applications the world of 3D graphics is rapidly expanding from desktop computers and dedicated gaming consoled to handheld devices, such as cellular phones, PDAs, laptops etc.,. However, unlike traditional desktop computers and gaming consoles, mobile computing devices typically have slower processors that have less capability for handling large computation-intensive workloads like 3D graphics application. In addition, the power consumption is one of the major design specifications to realize the 3D graphics accelerating engine for mobile devices because handheld batteries have limited lifetimes. Moreover, the size of chip is depend on the Moore¡¦s Law: The number of transistors in a chip are double in every eighteen months. Even though the produce cost is decrease, but the capacity of battery cannot increase like the transistors. Therefore, how to reduce power consumption by using efficient power management techniques has become a very important research topic in 3D graphics SoC design. For 3D graphics applications, dynamic voltage and frequency scaling (DVFS) is a good candidate to reduce the power consumption of 3D graphics accelerating engine. So many relative papers have researched in how to accurately predict the workload and scale the voltage and frequency. The prediction policy can divide into History-based predictor [1] and Frame-structure predictor [2-4]. The History-based predictor predicts the latter frame workload by previous frame workload to scale the voltage, and the frame-structure predictor performs offline and then determine the different kind of frame for an application. A table is used to save the mapping of different kind of frame to the voltage, and then the voltage is scaled according to the mapping table. A lot of researchers put the power management policy in software i.e. processors, but our proposed workload prediction scheme has been realized into the hardware circuit. Therefore, it can not only reduce the overhead of processor but also quickly adjust the voltage and frequency of 3D graphics accelerating engine. Our prediction policy is one of the History-based predictor ,and it is an adaptive PID predictor [5-6] in which the parameters of Proportional controller and Integral controller can be adaptively adjusted so that it can obtain more accurate prediction results than non-adaptive predictor. In general, the workload that the selected voltage can handle is usually over than the predicted workload. That is, actual workload is usually less than predicted workload. So that the slack time will be generated. We can utilize the slack time through Inter-frame compensation [7-10] to save more energy while maintaining the similar output quality. We use a simple policy to adaptively select the parameters for compensation between the frames to simplify the hardware architecture of the power management policy. Experimental results show that, we can get more energy saving and more accurate workload prediction when the adaptive PI predictor and adaptive Inter-frame compensation are utilized.