Rapid advancement in wireless communications over the years has been the driving force for many novel technologies providing compact and low cost solutions. Recent development of multilayer coplanar waveguide (CPW) MMIC technology promises realization of 3D MMIC in which large area-occupying passive components are translated from horizontal into vertical configuration resulting compact structure. The other main advantages of this technology are elimination of via-holes and wafer-thinning giving alternative performance solution, if not better, from the traditional MMIC. In this thesis, thermal and small-signal characteristics of prefabricated AlGaAs/InGaAs pseudomorphic high electron mobility transistors (pHEMTs) on semi-insulating (S.I.) GaAs substrate incorporated in the 3D MMIC technology have been analysed and modelled for the first time. A comprehensive small-signal parameter extraction procedure has been successfully developed which automatically determines the device small-signal parameters directly from the measured S-parameters. The developed procedure is unique since it provides a great deal of data on measured devices over a wide bias, temperature and frequency range for future incorporation of different active devices for the 3D MMIC technology and provides a first hand knowledge of how the multilayer structure will affect the performance of pre-fabricated pHEMTs. The extracted small-signal models of both pre- and post- multilayer processed pHEMTs have been compared and validated to the RF S-parameters measurements. The main focus was drawn upon the temperature dependent model parameters and how the underlying physics of the transistors behave in response to the change of temperature. These novel insights are especially valuable for devices designed specifically for high power applications like power amplifiers where tremendous heat could be generated. The data can also be interpreted as a way to optimise the multilayer structure, for example, alternative material with different properties can be implemented. The governing physics affecting device performance are also modelled and discussed empirically in details through extracted device parameters. These investigations would assist in the development of reliable, efficient and low cost production of future compact 3D multilayer CPW MMICs.

Electrostatic Discharge (ESD), as a subset of Electrical Overstress (EOS), was reported to be in charge of more than 35% of failure in integrated circuits (ICs). Especially in the manufacturing process, the silicon wafer turns out to be a functional ICs after numerous physical, chemical and mechanical processes, each of which expose the sensitive and fragile ICs to ESD environment. In normal end-user applications, ESD from human and machine handling, surge and spike signals in the power supply, and wrong supplying signals, will probably cause severe damage to the ICs and even the whole systems. Generally, ESD protections are evaluated after wafer and even system fabrication, increasing the development period and cost if the protections cannot meet customer's requirements. Therefore, it is important to design and customize robust and area-efficient ESD protections for the ICs at the early development stage. As the technologies generally scaling down, however, ESD protection clamps remain comparable area consumption in the recent years because they provide the discharging path for the ESD energy which rarely scales down. Diode is the most simple and effective device for ESD protection in ICs, but the usage is significantly limited by its low turn-on voltage. MOS devices can be triggered by a dynamic-triggered RC circuit for IOs operating at low voltage, while the one triggered by a static-triggered network, e.g., zener-resistor circuit or grounded-gate configuration, provides a high trigger voltage for high-voltage applications. However, the relatively low current discharging capability makes MOS devices as the secondary choice. Silicon-controlled rectifier (SCR) has become famous due to its high robustness and area efficiency, compared to diode and MOS. In this dissertation, a comprehensive design methodology for SCR based on simulation and measurement are presented for different advanced commercial technologies. Furthermore, an ESD clamp is designed and verified for the first time for the emerging GaN technology. For the SCR, no matter what modification is going to be made, the first concern when drawing the layout is to determine the layout geometrical style, finger width and finger number. This problem for diode and MOS device were studied in detail, so the same method was usually used in SCR. The research in this dissertation provides a closer look into the metal layout effect to the SCR, finding out the optimized robustness and minimized side-effect can be obtained by using specific layout geometry. Another concern about SCR is the relatively low turn-on speed when the IOs under protection is stressed by ESD pulses having very fast rising time, e.g., CDM and IEC 61000-4-2 pulses. On this occasion a large overshoot voltage is generated and cause damage to internal circuit component like gate oxides of MOS devices. The key determination of turn-on speed of SCR is physically investigated, followed by a novel design on SCR by directly connecting the Anode Gate and Cathode Gate to form internal trigger (DCSCR), with improved performance verified experimentally in this dissertation. The overshoot voltage and trigger voltage of the DCSCR will be significantly reduced, in return a better protection for internal circuit component is offered without scarifying neither area or robustness. Even though two SCR's with single direction of ESD current path can be constructed in reverse parallel to form bidirectional protection to pins, stand-alone bidirectional SCR (BSCR) is always desirable for sake of smaller area. The inherent high trigger voltage of BSCR that only fit in high-voltage technologies is overcome by embedding a PMOS transistor as trigger element, making it highly suitable for low-voltage ESD protection applications. More than that, this modification simultaneously introduces benefits including high robustness and low overshoot voltage. For high voltage pins, however, it presents another story for ESD designs. The high operation voltages require that a high trigger voltage and high holding voltage, so as to reduce the false trigger and latch-up risk. For several capacitive pins, the displacement current induced by a large snapback will cause severe damage to internal circuits. A novel design on SCR is proposed to minimize the snapback with adjustable trigger and holding voltage. Thanks to the additional a PIN diode, the similar high robustness and stable thermal leakage performance to SCR is maintained. For academic purpose of ESD design, it is always difficult to obtain the complete process deck in TCAD simulation because those information are highly confidential to the companies. Another challenge of using TCAD is the difficulty of maintaining the accuracy of physics models and predicting the performance of the other structures. In this dissertation a TCAD-aid ESD design methodology is used to evaluate ESD performance before the silicon shuttle. GaN is a promising material for high-voltage high-power RF application compared to the GaAs. However, distinct from GaAs, the leaky problem of the schottky junction and the lack of choice of passive/active components in GaN technology limit the ESD protection design, which will be discussed in this dissertation. However, a promising ESD protection clamp is finally developed based on depletion-mode pHEMT with adjustable trigger voltage, reasonable leakage current and high robustness.

Ce travail est une contribution à la conception de diviseurs de fréquence analogiques réalisés en technologie monolithique à base de transistors pseudomorphiques à haute mobilité électronique aux fréquences micro-ondes. Après avoir décrit les divers circuits existants en choisissant une classification originale selon les différents principes régissant la division de fréquence, nous développons une approche analytique basée sur des modèles simplifiés afin de trouver les paramètres essentiels du phénomène. Nous expérimentons également diverses méthodes d'analyse sur calculateur avec pour objectif le développement d'une approche méthodologique générale. Finalement, la méthode dite "de la boucle ouverte" est choisie pour la conception de circuits. Lors de son utilisation, il est à noter que des processus proches de cascades de bifurcations chaotiques sont observés. Une étude complémentaire présentée permet de vérifier qu'ils ne sont pas directement liés à la stabilité (physique) du dispositif. Ces travaux de modélisation sont pour la suite appliqués à la conception de deux diviseurs en technologie monolithique. Une large bande de synchronisation d'environ 30 % a été obtenue avec une topologie originale utilisant un transistor non polarisé sur le drain. Les résultats expérimentaux sont ensuite comparés aux simulations effectuées précédemment ainsi qu'aux performances déjà publiées sur des circuits de ce type. Enfin, une dernière partie est consacrée au bruit de phase dans les diviseurs de fréquences.

Ultra-broadband Monolithic Microwave Integrated Circuit (MMIC) amplifiers find applications in multi-gigabit communication systems for 5G and millimeter wave measurement instrumentation systems. The aim of the research was to achieve maximum bandwidth of operation of the amplifier from the foundry process used and high reverse isolation ( < -25.0 dB) across the whole bandwidth. To achieve this, several design variations of DC - 110 GHzMMIC Cascode TravellingWave Amplifier (TWA) on 100 nm AlGaAs/GaAs pHEMT process were done for application in next generation instrumentation and high data transfer rate (100 Gb/s) optical modulator systems. The foundry service and device models used for the design are of the WINPP10-10 process from WIN Semiconductor Corp., Taiwan, a commercial and highly stable process. The cut-off frequency ft and maximum frequency of oscillation fmax for this process are 135 GHz and 185 GHz respectively. Thus, the design was aimed at pushing the ultimate limits of operation for this process. The design specifications were targeted to have S21 = 9.0 to 10.0 ± 1.0 dB, S11 & S22 ≤ -10.0 dB and S12 ≤ -25.0 dB in the whole frequency range. In order to achieve the targeted RF performance, it is imperative to have accurate transistor models over the frequency range of operation, transistor configuration mode and operating bias points. Using smaller periphery transistors results in lower extrinsic & intrinsic input and output capacitances that lead to achieving very wide band performance. Thus, device sizes as small as 2x10 μm were used for the design. A cascode topology, which is a series connection of a common-source and common-gate field effect transistor (FET), was used to achieve large bandwidth of operation, high reverse isolation and high input and output impedance. Using very small periphery devices at cascode bias points posed limitation in the design in terms of accuracy of transistor models under these conditions, specifically at high frequencies i.e., above 50 GHz. One of the major systemrequirements for the application of MMIC ultra-broadband amplifiers in instrumentation is to achieve and maintain high reverse isolation (≤ -25.0 dB) over the whole frequency range of operation which cannot be achieved alone by the cascode topology and new design techniques have to be devised. These twomajor challenges, namely high frequency small periphery FET model modification & development and design technique to achieve high reverse isolation in ultra-broadband frequency range have been addressed in this research.

The Square Kilometre Array (SKA) is known to be the most powerful radio telescope of its type. In support of its high observational power, it is estimated that thousands of antenna unit equipped with millions of LNA (low noise amplifier) will be deployed over a large area (radius>3000km). The stringent requirements for high performance and low cost LNA design bring about many challenges in terms of material growth, device fabrication and low noise circuit designs. For the past decade, the Manchester group has been wholeheartedly committed to the research and development of high performance, low cost Monolithic Microwave Integrated Circuit (MMIC) LNA with high breakdown (15V) and low noise characteristics (1.2dB to 1.5dB) for the SKA mid-frequency application (0.4GHz to 1.4GHz). The on-going optimisation of current design is hindered by the restriction of standard i-line 1µm gate lithography. The primary focus of this work is on the design and fabrication of new, submicron gate InGaAs/InAlAs/InP pHEMTs for high frequency applications and future SKA high frequency bands. The study starts with the design and fabrication of InGaAs-InAlAs pHEMT sub-100nm gate structure using E-Beam lithography. To address the problems of short channel effect and parasitic components, devices with 128nm T-gate structure, and with optimised device geometries and enhanced material growth, having fT of 162GHz and fmax of 183GHz are demonstrated, outlining the importance of device scaling for high speed operation. In addition, a gate-sinking technique using Pd/Ti/Au metallisation scheme was investigated to meet the requirement for single voltage supply in circuit design. Device with Pd-buried gate exhibits enhanced DC and RF characteristics and showed no degradation over 5 hours’ annealing at 230˚C. The implementation of this highly thermal stable Pd Schottky gate is key to improving the device’s long-term reliability at high-temperature operation. To solve the problem of low productivity in E-Beam lithography, a simple, low cost, technique termed soft reflow was introduced by utilising the principle of solvent vaporisation in a closed chamber. It provides a hybrid solution for the fabrication of submicron device using low cost i-line lithography. The integration of this new soft reflow process with the Pd-gate sinking technique has enabled the large-scale fabrication of 250nm T-gate pHEMTs, with excellent fT of 108GHz and a fmax of 119GHz and with device yields exceeding 80%. This novel soft reflow technique provides a high yield, fast throughput, solution for the fabrication of submicron gate pHEMT and other ultra-high frequency nanoscale devices.

The largest 21st century radio telescope, the Square Kilometre Array (SKA) is now being planned, and the first phase of construction is estimated to commence in the year 2016. Phased array technology, the key feature of the SKA, requires the use of a tremendous number of receivers, estimated at approximately 37 million. Therefore, in the context of this project, the Low Noise Amplifier (LNA) located at the front end of the receiver chain remains the critical block. The demanding specifications in terms of bandwidth, low power consumption, low cost and low noise characteristics make the LNA topologies and their design methodologies one of the most challenging tasks for the realisation of the SKA. The LNA design is a compromise between the topology selection, wideband matching for a low noise figure, low power consumption and linearity. Considering these critical issues, this thesis describes the procedure for designing a monolithic microwave integrated circuit (MMIC) LNA for operation in the mid frequency band (400 MHz to 1.4 GHz) of the SKA. The main focus of this work is to investigate the potential of MMIC LNA designs based on a novel InGaAs/InAlAs/InP pHEMT developed for 1 µm gate length transistors, fabricated at The University of Manchester. An accurate technique for the extraction of empirical linear and nonlinear models for the fabricated active devices has been developed. In addition to the linear and nonlinear model of the transistors, precise models for passive devices have also been obtained and incorporated in the design of the amplifiers. The models show excellent agreement between measured and modelled DC and RF data. These models have been used in designing single, double and differential stage MMIC LNAs. The LNAs were designed for a 50 Ω input and output impedance. The excellent fits between the measured and modelled S-parameters for single and double stage single-ended LNAs reflects the accurate models that have been developed. The single stage LNA achieved a gain ranging from 9 to 13 dB over the band of operation. The gain was increased between 27 dB and 36 dB for the double stage and differential LNA designs. The measured noise figures obtained were higher by ~0.3 to ~0.8 dB when compared to the simulated figures. This is due to several factors which are discussed in this thesis. The single stage design consumes only a third of the power (47 mW) of that required for the double stage design, when driven from a 3 V supply. All designs were unconditionally stable. The chip sizes of the fabricated MMIC LNAs were 1.5 x 1.5 mm2 and 1.6 x 2.5 mm2 for the single and double stage designs respectively. Significantly, a series of differential input to single-ended output LNAs became of interest for use in the Square Kilometre Array (SKA), as it utilises differential output antennas in some of its configurations. The single-ended output is preferable for interfacing to the subsequent stages in the analogue chain. A noise figure of less than 0.9 dB with a power consumption of 180 mW is expected for these designs.

This doctoral thesis is focused on problems of modulators based on six-ports. It begins with description of current state of the art of six-ports used like modulators, their transfer functions and SIW technology. A design part of this thesis consists from experimental six-port based on substrate integrated waveguide (SIW) technology. There is presented step-by-step development of this six-port using this technology and also there is introduced micro-strip technology based six-port. Final design of six-ports and variable impedances were measured, the results are discussed and compared with expected ones in next chapters. Second part of this thesis deals with influences of internal parameters of six-ports to final signal transmission and derives theirs transfer functions for more than one reflection in structure. The computation results are compared with experimental measurements for fixed loads. With using of ideal loads sweeps, modulations with shaped input signals were calculated. For designed variables impedances, there was founded the optimal biasing points for demanded IQ diagram and discussed which from tested active circuit is suitable. In the last part there are shown results of experiment with these variable loads connected to both types of designed six-ports.

L'augmentation des débits à 10Gbps et 40Gbps dans les télécommunications<br />optiques couplée à des besoins de portées supérieures à 150 km privilégie l'emploi de la<br />modulation externe, et en particulier, des modulateurs électro-optiques. Les circuits de<br />commande des modulateurs optiques apparaissent alors comme un élément clé de ces<br />systèmes de transmission.<br />Les premiers chapitres permettent, suite à une présentation des systèmes et architectures les<br />plus couramment utilisés, de définir les spécifications en performances requises pour les<br />circuits de commande de modulateurs externes et en particulier des modulateurs électrooptiques.<br />Une étude complète des amplificateurs distribués, et de leurs différentes<br />configurations, est menée. Ces amplificateurs, par leur produit gain-bande passante élevé,<br />répondent en effet au mieux aux exigences définies. Les amplificateurs conçus ont été réalisés<br />à partir de transistors PHEMT sur arséniure de gallium, de 0.15 μm de longueur de grille.<br />Afin de simplifier la mise en boîtier et de résoudre les désagréments de la polarisation<br />classique des amplificateurs distribués, deux nouveaux circuits de polarisation intégrés ont été<br />développés. Tout d'abord une nouvelle charge active, tenant lieu de terminaison de la ligne de<br />sortie de l'amplificateur distribué, permet de polariser et de conserver l'adaptation en sortie de<br />l'amplificateur distribué lors d'une variation du courant de polarisation, pour d'un contrôle de<br />gain par exemple. Egalement un dispositif intégré de sources de courant connectés à la ligne<br />de sortie de l'amplificateur distribué, appelé té de polarisation actif, a été étudié. La<br />réalisation d'un circuit de commande, par le report et la mise en boîtier d'un amplificateur<br />distribué utilisant le té de polarisation actif, a été validée par des mesures de paramètres [S] et<br />des diagrammes de l'oeil électriques et optiques.

The Square Kilometre Array (SKA) is a multibillion and a multinational science project to build the world’s largest and most sensitive radio telescope. For a very large field of view, the combined collecting area would be one square kilometre (or 1, 000, 000 square metre) and spread over more than 3,000 km wide which will require a massive count of antennas (thousands). Each of the antennas contains hundreds of low noise amplifier (LNA) circuits. The antenna arrays are divided into low, medium and high operational frequencies and located at different positions to boost up the telescope’s scanning sensitivity.The objective of this work was to develop and fabricate fully on-chip LNA circuits to meet the stringent requirements for the mid-frequency array from 0.4 GHz to 1.4 GHz of the SKA radio astronomy telescope using Monolithic Microwave Integrated Circuit technology (MMIC). Due to the number of LNA reaching figures of millions, the fabricated circuits were designed with the consideration for low cost fabrication and high reliability in the receiver chain. Therefore, a relaxed optical lithography with Lg = 1 µm was adopted for a high yield fabrication process.Towards the fulfilment of the device’s low noise characteristics, a large number of device designs, fabrication and characterisation of InGaAs/InAlAs/InP pHEMTs were undertaken. These include optimisations at each critical fabrication steps. The device’s high breakdown and very low gate leakage characteristics were further improved by a combination of judicious epitaxial growth and manipulation of materials’ energy gaps. An attempt to increase the device breakdown voltage was also employed by incorporating Field Plate structure at the gate terminal. This yielded the devices with improvements in the breakdown voltage up to 15 V and very low gate leakage of 1 µA/mm, in addition to high transconductance (gm) characteristic. Fully integrated double stage LNA had measured NF varying from 1.2 dB to 1.6 dB from 0.4 GHz to 1.4 GHz, compared with a slightly lower NF obtained from simulation (0.8 dB to 1.1 dB) across the same frequency band.These are amongst the attractive device properties for the implementation of a fully on-chip MMIC LNA circuits demonstrated in this work. The lower circuit’s low noise characteristic has been demonstrated using large gate width geometry pHEMTs, where the system’s noise resistance (Rn) has successfully reduced to a few ohms. The work reported here should facilitate the successful implementation of rugged low noise amplifiers as required by SKA receivers.

No description available.