Majority of the modern day compute intensive applications are heterogeneous in nature. To support their ever increasing computational requirements, present day System-on-Chip (SoC) architectures have adapted multicore style of modeling, thereby incorporating multiple, heterogeneous processing cores on a single chip. The emerging Network-On-Chip (NoC) interconnect paradigm provides a scalable and power-efficient solution for communication among multiple cores, serving as a powerful replacement for traditional bus based architectures. A fast, robust and exible emulation platform is the key to successful realization and validation of such architectures within a very short span of time. This research focuses on various aspects of Hardware/Software (HW/SW) codesign for AcENoCs (Accelerated Emulation Platform for NoCs), a Field Programmable Gate Array (FPGA) accelerated, con gurable, cycle accurate platform for emulation and validation of NoC architectures. This work also details the design, implementation and evaluation of AcENoCs' software framework along with the various design optimizations carried out and tradeoffs considered in AcENoCs' HW/SW codesign for achieving an optimum balance between emulated network dimensions and emulation performance. AcENoCs emulation platform is realized on a Xilinx Virtex-5 FPGA. AcENoCs' hardware framework consists of the NoC built using configurable hardware library components, while the software framework consists of Traffic Generators (TGs) and their associated source queues, Traffic Receptors (TRs) along with statistics analysis module and dynamically controlled emulation clock generator. The software framework is implemented using on-chip Xilinx MicroBlaze processor. This report also describes the interaction between various HW/SW events in an emulation cycle and assesses AcENoCs' performance speedup and tradeoffs over existing FPGA emulators and software simulators. FPGA synthesis results showed that networks with dimensions upto 5x5 could be accommodated inside the device. Varying synthetic traffic workloads, generated by TGs, were used to evaluate the network. Real application based traces were also run on AcENoCs platform to evaluate the performance improvement achieved in comparison to software simulators. For improving the emulator performance, software profiling was carried out to identify and optimize the software components consuming highest number of processor cycles in an emulation cycle. Emulation testcases were run and latency values recorded for varying traffic patterns in order to evaluate AcENoCs platform. Experimental results showed emulation speedups in order of 10000-12000X over HDL (Hardware Description Language) simulators and 14-47X over software simulators, without sacri cing cycle accuracy.

The thesis uses the case study of software industry development to investigate the role of the state, relationship with the private sectors, and its transformation. Besides, This paper adopts Peter Evans¡¦ ¡§embedded autonomy¡¨ and Linda Weiss¡¦s ¡§governed interdependence theory¡¨ to explain these situations. As far as Taiwan, the state helped develop software industry after 1980s. At that time, there was no software programming or service company in Taiwan. Like the other strategy industry, the state set up the pilot agency, III, to support software industry, but the state didn¡¦t intervene in production. The unique character of software industrial development has been its synchronized globalization among developed and developing world. To out-compete among others in software industry is quite a gap for Taiwan. Besides, Taiwan¡¦s labor cost is higher then India and Mainland China. So, Taiwan has no chance to get the low-level business. In the analysis, the state¡¦s e-government budget didn¡¦t benefit to software industry. The state have no obvious network with society, have no control force to software private sectors, and the state¡¦s capacity was be doubted. So the state only just plays a ¡§husbandry¡¨ ideal-type.

The topic of stereo video is getting more attention among these days due to its high quality of visual effect. However, the large volume of data is the problem of its application. The topic of this thesis is to investigate a compression technique by Wavelet compression on the stereo video data. There is much similarity between the parallax videos. This similarity is obtained by a motion compensation technique: the optical flow computing. Optical flow proposed by Horn and Schunck was originally developed in the field of computer vision for the application of moving detection. In this thesis we apply the optical flow to compress the similarity information between the parallax stereo video. On the other hand, the Wavelet transformation has been proved to be a successful technique for multiscale modeling. We therefore applying the Wavelet transform combined with the zerotree compression to compress the fields of optical flow. Experimental results in this thesis have demonstrated different effects in different situations.

The thesis is mainly divided into three parts. The first part will discuss about structures, manufacture, and design flow of embedded passives in organic and flexible substrates, and the results of measurement and electromagnetic (EM) simulation will be compared as well. Second part will discuss the theory and the process of establishing broadband model, and the broadband model will be compared to Pi model and EM simulation. In the third part, we will try to design embedded bandpass filters in organic substrate by the experience of establishing the library of embedded passives. Because of lacking of the fabrication of large capacitance devices in organic substrate, we design bandpass filters by using T type in order to limit the lump devices in the larger inductance and smaller capacitance. The final result of the filters are small in size and have high performance, thus they can be well applied to the RF system in chip (SIP) of wireless communication.

This thesis presents a new cross-platform graphics performance tool, GPTT (Graphics Performance Tuning Tool), which is designed for helping developers to find the performance bottleneck of their games or applications on embedded systems. The functions of performance tool are embedded into the standard graphics library, OpenGL ES, to achieve cross-platform. In order to verify the proposed tool, we also implement the OpenGL ES specification in addition to the tool itself. The performance tool is separated into visualization part and measurement part from which it successfully decreases the load in embedded system, while running the application. Via the tool it identifies many bottlenecks that can be improved.

The paper proposes that Embedded Zreotree Wavelet algorithm and the architecture of the modified EZW algorithm will have the property of regularity, modularity ,and scalablity, and also posses the function , which can allow a detected watermark to be embedded. The methods to realize the algorithm and the function of watermark are to analyze the theory of algorithm and the order of output and input data and then to use queue and stack, the unit of memory, and the control of circuit. The modified EZW architecture needs a half less memory units than the original one, and functions nearly as effective as the original architecture. Besides, this paper points out that the whole architecture of the transform CODEC system can be applied properly to HDTV, MPEG-4 system, or QoS network.

We proposes an efficient algorithm for extracting SPICE-compatible circuits of embedded interconnect structures from FDTD-simulated time-domain reflections. A layer-peeling technique (LPT) is used to obtain the time-domain step response of the interconnects under extract (IUE) itself. A pencil matrix method is then used to get the pole-residue representation of the time-domain step response of the IUE. A pole-reducing procedure is implemented based on a bandwidth criterion to simplify pole-residue representation. Finally, the lumped equivalent models of the IUE are synthesized by an equivalent lumped-model extraction technique, in which four types of equivalent model bases are used. The equivalent circuit can be easily implemented in SPICE-like simulator. Several transmission line structures are presented as examples to demonstrate the validity of the proposed algorithm both in time and frequency domains.

Technological advancements in computer hardware and software have made embedded systems highly affordable and widely used. Consumers have ever increasing demands for powerful embedded devices such as cell phones, PDAs and media players. Such complex and feature-rich embedded devices are strictly limited by their battery life- time. Embedded systems typically are diskless and use flash for secondary storage due to their low power, persistent storage and small form factor needs. The energy efficiency of a processor and flash in an embedded system heavily depends on the choice of file system in use. To address this problem, it is necessary to provide sys- tem developers with energy profiles of file system activities and energy efficient file systems. In the first part of the thesis, a macro-model for the CRAMFS file system is established which characterizes the processor and flash energy consumption due to file system calls. This macro-model allows a system developer to estimate the energy consumed by CRAMFS without using an actual power setup. The second part of the thesis examines the effects of using non-volatile memory as a write-behind buffer to improve the energy efficiency of JFFS2. Experimental results show that a 4KB write-behind buffer significantly reduces energy consumption by up to 2-3 times for consecutive small writes. In addition, the write-behind buffer conserves flash space since transient data may never be written to flash.

eBay chief executive, Meg Whitman, at a press conference expressed to the investors that ¡§communications plays a key role in e-commerce and society. This makes Skype become the most suitable cooperator with eBay.¡¨ When integrating with Skype, eBay makes buyers and sellers communicate with each other through VoIP. This removes the biggest obstacle between buyers and sellers and achieves an ¡§unparalleled e-commerce and communications engine.¡¨ ¡§eBay with Skype¡¨ is the best example of 3PCC with e-commerce. 3PCC is a model that allows an entity (which is called controller) to manage and set up a communication between two or more other parties. It has already existed in the PSTN for a long time. Although there are many applications designed for SIP, they are not 3PCC with e-commerce model. Therefore, we attempt to design an application that integrating 3PCC with e-commerce. In this paper, we not only introduce how 3PCC is achieved but also express how REFER (a new method in SIP) can be used for replacing the traditional 3PCC mechanism in chapter 2. Chapter 3 will introduce the S/H development framework, the flows of SIP and the functions or libraries related to the Gateway. In chapter 4, we will first explain the design concept about our systems and then express how we implement the system. These include the website database structures, the Gateway programs and the packet analysis and verification. Finally, we will conclude this paper in Chapter 5. In addition, we will show the system and operation guide in appendix.

The epicyclic gear mechanisms are widely used in the automatic transmissions for automobiles, and can provide several speed ratios by the controls of the input and fixed links with clutches and brakes. In order to increase the number of speed ratios, two or three embedded clutches are adapted in the automatic transmissions. However, the design of automatic transmissions with one embedded clutch has been hitherto ignored. Thus, the purpose of this work is to develop a systematic methodology for the design of automobiles automatic transmissions with one embedded clutch. First, the design specifications are established based on the requirements of the epicyclic automatic transmissions. Next, a procedure of the conceptual synthesis is developed to enumerate the epicyclic gear mechanisms with one embedded clutch. The corresponding atlas of the epicyclic gear mechanisms with two fundamental geared entities are established. Finally, a method is created to arrange the clutches and brakes into epicyclic gear mechanisms. Then the numbers of the teeth of gears are calculated by an analytical way. The result of this research shows that five five-speed automatic transmission and one seven-speed automatic transmission are synthesized. The associated efficiency for each speed is greater than 95%. This demonstrates the feasibility of the proposed methodology.