This thesis presents design automation methodologies for extensible processor platforms in application specific domains. The work presents first a single processor approach for customization; a methodology that can rapidly create different processor configurations by the removal of unused instructions sets from the architecture. A profile directed approach is used to identify frequently used instructions and to eliminate unused opcodes from the available instruction pool. A coprocessor approach is next explored to create an SoC (System-on-Chip) to speedup the application while reducing energy consumption. Loops in applications are identified and accelerated by tightly coupling a coprocessor to an ASIP (Application Specific Instruction-set Processor). Latency hiding is used to exploit the parallelism provided by this architecture. A case study has been performed on a JPEG encoding algorithm; comparing two different coprocessor approaches: a high-level synthesis approach and our custom coprocessor approach. The thesis concludes by introducing a heterogenous multi-processor system using ASIPs as processing entities in a pipeline configuration. The problem of mapping each algorithmic stage in the system to an ASIP configuration is formulated. We proposed an estimation technique to calculate runtimes of the configured multiprocessor system without running cycle-accurate simulations, which could take a significant amount of time. We present two heuristics to efficiently search the design space of a pipeline-based multi ASIP system and compare the results against an exhaustive approach. In our first approach, we show that, on average, processor size can be reduced by 30%, energy consumption by 24%, while performance is improved by 24%. In the coprocessor approach, compared with the use of a main processor alone, a loop performance improvement of 2.57x is achieved using the custom coprocessor approach, as against 1.58x for the high level synthesis method, and 1.33x for the customized instruction approach. Energy savings are 57%, 28% and 19%, respectively. Our multiprocessor design provides a performance improvement of at least 4.03x for JPEG and 3.31x for MP3, for a single processor design system. The minimum cost obtained using our heuristic was within 0.43% and 0.29% of the optimum values for the JPEG and MP3 benchmarks respectively.

[Truncated abstract] The feasibility of using interlocked light gauge sheet piles to form a deep cross-sectional wall embedded in a residual slope or with a berm support is explored. This thesis compares the performance of a large section modulus sheet pile wall as an alternative to a concrete diaphragm wall, acting as an embedded cantilever wall on a slope (ECWS) by means of experimental centrifuge tests, numerical models and analytical methods. Abaqus (Hibbitt, Karlsson and Sorensen Inc, 1997) was used to conduct extensive numerical trials on the structural performance of the sheet pile wall model prior to the actual physical testing. The Abaqus results showed that the integrity of the interlock and reduced modulus action (RMA) due to slippage along the interlocked joint did not cause premature buckling of the thin wall even at the ultimate load. Further, a comparative study using centrifuge tests on 1:30 scaled models and Plaxis analysis demonstrated that under the worst condition with high water table, the rigid sheet pile wall of 1.32 m cross-sectional width carried a higher ultimate surcharge load with a much lower top of wall deflection, compared to a more flexible 0.6 m thick cracked concrete diaphragm wall. The analysis of the wall/soil/slope interactions for an ECWS involves many inter-dependent variables in addition to the complications of considering an adjacent slope or a berm support. It is difficult for existing analytical approaches to take all these factors into account, and some form of numerical analysis, calibrated through field data and results from centrifuge model tests is necessary. From the observations of the centrifuge tests and finite element analysis, major assumptions about the failure of a stiff ECWS in a rotational mode were deduced and adopted in the proposed limiting equilibrium method (Leq). The plane strain Leq ECWS Abstract ii analysis is based on the framework of minimum upper bound limiting equilibrium with planar failure planes and a Mohr-Coulomb soil model. As compared to the traditional limit equilibrium analysis, the Leq method is a fully coupled analysis using the shear strength reduction technique (SSR). New formulations are proposed for the development of horizontal active and passive pressure distributions based on the experimental and FE models. The proposed active pressure profile used is derived by combining the Coulomb and Krey method, and empirically back-figured to curve-fit the centrifuge tests by Morris (2005). The proposed passive pressure profile of a rigid rotational wall in failure is adjusted to allow for an adjacent slope or berm support through a presumed elasto-plastic deformation instead of a linear rigid translation of the passive wedge. ... A parametric study was later undertaken using the Leq method to develop a series of non-dimensionalised graphs to study and draw summarised conclusions on the behaviour of the ECWS. The final conclusions on the comparative study of the centrifuge tests, Plaxis and Leq analyses demonstrated that the alternative light gauge steel sheet pile performed very well as an ECWS. A key factor in the performance of the sheet pile wall was attributed to the large 1.32 m cross-sectional width of the interlocked sections. This provided high bending stiffness and high moment stability from shear stresses acting on the back and front faces of the wall.

As embedded systems designers increasingly turn to programmable logic technologies in place of off-the-shelf microprocessors, there is a growing interest in the development of optimised custom processing cores that can be designed on a per-application basis. FPGAs blur the traditional distinction between hardware and software and offer the promise of application specific hardware acceleration. But realizing this in a general sense requires a significant departure from traditional embedded systems development flows. Whereas off-the-shelf processors have a fixed architecture, the same cannot be said of purpose-built FPGA-based processors. With this freedom comes the challenge of empirically determining the optimal boundary point between hardware and software. The fluidity of the hardware/software partition also poses an interesting challenge for compiler developers. This thesis presents a tool and methodology that addresses these codesign challenges in a new way. Described as 'compiler-directed codesign', it makes use of a suitably modified compiler to help direct the development of a custom processor core on a per-application basis. By exposing the compiler's internal representation of a compiled target program, visibility into those instructions, and hardware resources, that are most sought after by the compiler can be gained. This information is then used to inform further processor development and to determine the optimal partition between hardware and software. At each design iteration, the machine model is updated to reflect the available hardware resources, the compiler is rebuilt, and the target application is compiled once again. By including the compiler 'in-the-loop' of custom processor design, developers can accurately quantify the impact on performance caused by the addition or removal of specific hardware resources and iteratively converge on an optimal solution. Compiler Directed Codesign has advantages over existing codesign methodologies because it offers both a concrete point from which to begin the partitioning process as well as providing quantifiable and rapid feedback of the merits of different partitioning choices. When applied to an Adaptive PCM Encoder/Decoder case study, the Compiler Directed Codesign technique yielded a custom processor core that was between 36% and 73% smaller, consumed between 11% to 19% less memory, and performed up to 10X faster than comparable general-purpose FPGA-based processor cores. The conclusion of this work is that a suitably modified compiler can serve a valuable role in directing hardware/software partitioning on a per-application basis.

AADL est dédié à la conception de haut niveau et l'évaluation de systèmes embarqués. Il permet de décrire la structure d'un système et ses aspects fonctionnels par une approche à base de composants. Des processus localement synchrones sont alloués sur une architecture distribuée et communiquent de manière globalement asynchrone (système GALS). Une spécificité du modèle polychrone est qu'il permet de spécifier un système dont les composants peuvent avoir leur propre horloge d'activation : il est bien adapté à une méthodologie de conception GALS. Dans ce cadre, l'atelier Polychrony fournit des modèles et des méthodes pour la modélisation, la transformation et la validation de systèmes embarqués. Cette thèse propose une méthodologie pour la modélisation et la validation de systèmes embarqués spécifiés en AADL via le langage synchrone multi-horloge Signal. Cette méthodologie comprend la modélisation de niveau système en AADL, des transformations automatiques du modèle AADL vers le modèle polychrone, la distribution de code, la vérification formelle et la simulation du modèle polychrone. Notre transformation prend en compte l'architecture du système, décrite dans un cadre IMA, et les aspects fonctionnels, les composants logiciels pouvant être mis en œuvre en Signal. Les composants AADL sont modélisés dans le modèle polychrone en utilisant une bibliothèque de services ARINC. L'annexe comportementale d'AADL est interprétée dans ce modèle via SSA. La génération de code distribué est obtenue avec Polychrony. La vérification formelle et la simulation sont effectuées sur deux études de cas qui illustrent notre méthodologie pour la conception fiable des applications AADL.

<p>Events play an important role in many computer systems, from small reactive embedded applications to large distributed systems. Many applications react to events generated by a graphical user interface or by external sensors that monitor the system environment, and other systems use events for communication and synchronisation between independent subsystems. In some applications, however, individual event occurrences are not the main point of concern. Instead, the system should respond to certain event patterns, such as "the start button being pushed, followed by a temperature alarm within two seconds". One way to specify such event patterns is by means of an event algebra with operators for combining the simple events of a system into specifications of complex patterns.</p><p>This thesis presents an event algebra with two important characteristics. First, it complies with a number of algebraic laws, which shows that the algebra operators behave as expected. Second, any pattern represented by an expression in this algebra can be efficiently detected with bounded resources in terms of memory and time, which is particularly important when event pattern detection is used in embedded systems, where resource efficiency and predictability are crucial.</p><p>In addition to the formal algebra semantics and an efficient detection algorithm, the thesis describes how event pattern detection can be used in real-time systems without support from the underlying operating system, and presents schedulability theory for such systems. It also describes how the event algebra can be combined with a component model for embedded system, to support high level design of systems that react to event patterns.</p>

<p>Embedded systems are microprocessor-based systems that cover a large range of computer systems from ultra small computer-based devices to large systems monitoring and controlling complex processes. The particular constraints that must be met by embedded systems, such as timeliness, resource-use efficiency, short time-to-market and low cost, coupled with the increasing complexity of embedded system software, demand technologies and processes that will tackle these issues. An attractive approach to manage the software complexity, increase productivity, reduce time to market and decrease development costs, lies in the adoption of the component based software engineering (CBSE) paradigm. The specific characteristics of embedded systems lead to important design issues that need to be addressed by a component model. Consequently, a component model for development of embedded systems needs to systematically address extra-functional system properties. The component model should support predictable system development and as such guarantee absence or presence of certain properties. Formal methods can be a suitable solution to guarantee the correctness and reliability of software systems.</p><p> </p><p>Following the CBSE spirit, in this thesis we introduce the ProCom component model for development of distributed embedded systems. ProCom is structured in two layers, in order to support both a high-level view of loosely coupled subsystems encapsulating complex functionality, and a low-level view of control loops with restricted functionality. These layers differ from each other in terms of execution model, communication style, synchronization etc., but also in kind of analysis which are suitable. To describe the internal behavior of a component, in a structured way, in this thesis we propose REsource Model for Embedded Systems (REMES) that describes both functional and extra-functional behavior of interacting embedded components. We also formalize the resource-wise properties of interest and show how to analyze such behavioral models against them.</p> / PROGRESS

Progress

<p>The IEEE 802.11b standard is today the only commonly used standard in Europe for fast wireless networks. This makes it possible to connect computers to networks in places where it is not possible to use wires. Examples of such situations are internet access at airports, communication in emergency areas or for military communication. Common for all these situations is that network security is important. </p><p>This thesis consists of two different parts. The first part handles the security mechanisms and the second part is an evaluation of the possibilities to use IEEE 802.11b in embedded applications. The part that handles the security includes the security mechanisms found in the standard, flaws in these mechanisms and methods that try to reduce these problems.</p>

<p>In recent years, the drive for ever increasing energy efficiency has intensified. The main driving forces behind this development are the increased innovation and adoption of mobile battery powered devices, increasing energy costs, environmental concerns, and strive for denser systems.</p><p>This work is meant to serve as a foundation for exploration of energy conscious software. We present an overview of previous work and a background to energy concerns from a software perspective. In addition, we describe and test a few methods for decreasing energy consumption with emphasis on using software parallelism. The experiments are conducted using both a simulation environment and real hardware. Finally, a method for measuring energy consumption on a hardware platform is described.</p><p>We conclude that energy conscious software is very dependent on what hardware energy saving features, such as frequency scaling and power management, are available. If the software has a lot of unnecessary, or overcomplicated, work, the energy consumption can be lowered to some extent by optimizing the software and reducing the overhead. If the hardware provides software-controllable energy features, the energy consumption can be lowered dramatically.</p><p>For suitable workloads, using parallelism and multi-core technologies seem very promising for producing low power software. Realizing this potential requires a very flexible hardware platform. Most important is to have fine grained control over power management, and voltage and frequency scaling, preferably on a per core basis.</p>

<p>Communication and digital signal processing applications of today are often developed as fully integrated systems on one single chip and are implemented as application specific integrated circuits using e.g. VLSI technology. As the systems are getting more and more complex in terms of speed and performance the chip size and the design time tend to increase rapidly. This will result in search for cheaper and less time consuming alternatives. One alternative is field programmable gate arrays, so called FPGAs. The FPGAs are getting faster, cheaper and the number of gates increases all the time. A long list of ready to use functional blocks so called intellectual property (IP) blocks can be used in FPGAs. The latest FPGAs can also be bought with one or more embedded processors, in form of hard processor cores or as licenses for soft processor cores. This will speed up the design phase and of course also decrease the crucial time to market even more. </p><p>The purpose of this master’s thesis was to develop a waveform generator to generate a sine signal and a cosine signal, I and Q, used for radio/radar applications. The digital signals should have an output data rate of at least 100 MHz. The digital part of the system should be implemented in hardware using e.g. an FPGA. To convert the digital signals to analog signals two D/A converters are used. The analog signals, I and Q, should have a bandwidth of 1 MHz - 11 MHz. </p><p>The waveform generator was developed and implemented using a Virtex II FPGA from Xilinx. An embedded microprocessor within the FPGA, MicroBlaze, in form of a soft processor core was used to control the system. A user interface program running on the microprocessor was also developed. Testing of the whole system, both hardware and software, was done. The system is able to generate digital sine and cosine curves of an output data rate of 100 MHz.</p>